ADS5294
- Maximum Sample Rate: 80 MSPS/14-Bit
- High Signal-to-Noise Ratio
- 75.5-dBFS SNR at 5 MHz / 80 MSPS
- 78.2-dBFS SNR at 5 MHz / 80 MSPS and Decimation Filter Enabled
- 84-dBc SFDR at 5 MHz / 80 MSPS
- Low Power Consumption
- 58 mW/CH at 50 MSPS
- 77 mW/CH at 80 MSPS (2-LVDS Wire Per Channel)
- Digital Processing
Block
- Programmable FIR Decimation Filter and Oversampling to Minimize Harmonic Interference
- Programmable IIR High-Pass Filter to Minimize DC Offset
- Programmable Digital Gain: 0 dB to 12 dB
- 2-Channel or 4-Channel Averaging
- Flexible Serialized LVDS
Outputs:
- One or Two Wires of LVDS Output Lines Per Channel Depending on ADC Sampling Rate
- Programmable Mapping Between ADC Input Channels and LVDS Output Pins-Eases Board Design
- Variety of Test Patterns to Verify Data Capture by FPGA/Receiver
- Internal and External References
- 1.8-V Operation for Low Power Consumption
- Low-Frequency Noise Suppression
- Recovery From 6-dB Overload Within 1 Clock Cycle
- Package: 12-mm × 12-mm 80-Pin QFP
The ADS5294 is a low-power 80-MSPS 8-Channel ADC that uses CMOS process technology and innovative circuit techniques. Low power consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high-performance systems.
The digital processing block of the ADS5294 integrates several commonly used digital functions for improving system performance. The device includes a digital filter module that has built-in decimation filters (with lowpass, highpass and bandpass characteristics). The decimation rate is also programmable (by 2, by 4, or by 8). This rate is useful for narrow-band applications, where the filters are used to conveniently improve SNR and knock-off harmonics, while at the same time reducing the output data rate. The device includes an averaging mode where two channels (or even four channels) are averaged to improve SNR.
Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The digital data from each channel ADC is output over one or two wires of LVDS output lines depending on the ADC sampling rate. This 2-wire interface maintains a low serial-data rate, allowing low-cost FPGA-based receivers to be used even at a high sample rate. The ADC resolution is programmed to 12-bit or 14-bit through registers. A unique feature is the programmable-mapping module that allows flexible mapping between the input channels and the LVDS output pins. This module greatly reduces the complexity of LVDS-output routing, and by reducing the number of PCB layers, potentially results in cheaper system boards.
The device integrates an internal reference trimmed to accurately match across devices. Internal reference mode achieves the best performance. External references can also drive the device.
The device is available in a 12-mm × 12-mm 80-pin QFP package. The device is specified over a –40°C to 85°C operating temperature range. ADS5294 is completely pin-to-pin and register compatible to ADS5292.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | Octal-Channel 14-Bit 80-MSPS High-SNR and Low-Power ADC datasheet (Rev. E) | 2018. 4. 23 | ||
| 애플리케이션 노트 | High Speed ADCs and Amplifiers for Flow Cytometry Applications | 2020. 10. 12 | |||
| 애플리케이션 노트 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015. 5. 22 | |||
| 애플리케이션 노트 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013. 7. 19 | |||
| 애플리케이션 노트 | Understanding Serial LVDS Capture in High-Speed ADCs | 2013. 7. 10 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
ADS5294EVM — ADS5294 평가 모듈
ADS5294 평가 모듈(EVM)은 다양한 클록 및 입력 조건에서 ADS5294를 테스트할 수 있는 유연한 환경을 제공합니다. 이 EVM을 사용하면 자체 필터를 설계하고, EVM에 해당 부품을 채우고, EVM 자체에서 성능을 확인할 수 있습니다.
ADS5294EVM 평가를 위해 TSW1400EVM(구형)이 필요합니다. TSW1400EVM이 이미 있는 경우가 아니면 ADS5294EVM을 구매하지 않는 것이 좋습니다.
SLAC509 — ADS5294EVM GUI Installer
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
아날로그 엔지니어의 계산기는 아날로그 회로 설계 엔지니어가 정기적으로 사용하는 많은 반복 계산의 속도를 높이도록 설계되었습니다. 이 PC 기반 툴은 피드백 저항을 사용한 연산 증폭기 게인 설정부터 아날로그-디지털 컨버터(ADC) 드라이브 버퍼 회로 안정화를 위한 적절한 회로 설계 요소 선택에 이르기까지 다양한 일반적인 계산 목록이 포함된 그래픽 인터페이스를 제공합니다.
이 계산기는 독립 실행형 툴로 유용할 뿐만 아니라 아날로그 엔지니어의 포켓 레퍼런스에 설명된 개념과도 잘 어울립니다.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| HTQFP (PFP) | 80 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.