홈 데이터 컨버터 아날로그-디지털 컨버터(ADC) 고속 ADC(≥10 MSPS)
홈
데이터 컨버터
아날로그-디지털 컨버터(ADC)
고속 ADC(≥10 MSPS)

ADS62C15

활성

듀얼 채널, 11비트, 125MSPS 아날로그-디지털 컨버터(ADC)

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ADS62C15

활성
데이터 시트 지금 주문하기

제품 상세 정보

Sample rate (max) (Msps) 125 Resolution (Bits) 11 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 450 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 740 Architecture Pipeline SNR (dB) 67.2 ENOB (Bits) 10.8 SFDR (dB) 89 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 125 Resolution (Bits) 11 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 450 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 740 Architecture Pipeline SNR (dB) 67.2 ENOB (Bits) 10.8 SFDR (dB) 89 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 125 MSPS
  • 11-Bit Resolution With No Missing Codes
  • 82 dBc SFDR at Fin = 117 MHz
  • 67 dBFS SNR at Fin = 117 MHz
  • 77.5 dBFS SNR at Fin = 117 MHz, 20MHz bandwidth
    using technology
  • 92 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block With:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable 24-Tap Low/High/
      Band Pass Filters
  • Supports Sine, LVPECL, LVDS and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Also Supports External Reference
  • 64-QFN Package (9mm × 9mm)
  • Maximum Sample Rate: 125 MSPS
  • 11-Bit Resolution With No Missing Codes
  • 82 dBc SFDR at Fin = 117 MHz
  • 67 dBFS SNR at Fin = 117 MHz
  • 77.5 dBFS SNR at Fin = 117 MHz, 20MHz bandwidth
    using technology
  • 92 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block With:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable 24-Tap Low/High/
      Band Pass Filters
  • Supports Sine, LVPECL, LVDS and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Also Supports External Reference
  • 64-QFN Package (9mm × 9mm)

ADS62C15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62C15 uses proprietary technology that can be used to overcome SNR limitation due to quantization noise (for bandwidths less than Nyquist, Fs/2). It includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62C15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. The device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

ADS62C15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62C15 uses proprietary technology that can be used to overcome SNR limitation due to quantization noise (for bandwidths less than Nyquist, Fs/2). It includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62C15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. The device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).
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기술 자료

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13개 모두 보기
상위 문서 유형 직함 형식 옵션 날짜
* Data sheet Dual Channel 11-Bits, 125MSPS ADC With Parallel CMOS/DDR LVDS Outputs datasheet (Rev. E) 2012/02/09
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 2015/05/22
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 2013/07/19
User guide TSW4200 Demonstration Kit User's Guide (Rev. C) 2012/10/31
Application note Band-Pass Filter Design Techniques for High-Speed ADCs 2012/02/27
Application note Understanding Low-Amplitude Behavior of 11-bit ADCs 2011/10/22
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 2010/09/10
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 2009/04/28
User guide ADS62PxxEVM Quick Start Guide (Rev C Board) (Rev. A) 2009/04/02
Application note CDCE62005 as Clock Solution for High-Speed ADCs 2008/09/04
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 2008/06/08
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2008/06/02
Application note QFN Layout Guidelines 2006/07/28

설계 및 개발

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평가 모듈(EVM)용 GUI

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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HSADC-SPI-UTILITY — ADS5400 EVM GUI

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SBAC120 — TIGAR Support Files

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시뮬레이션 모델

ADS62Pxx Family TINA-TI Transient Reference Design

SBAM008.ZIP (6 KB) - TINA-TI Reference Design
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시뮬레이션 모델

ADS62Pxx Family TINA-TI Transient Spice Model

SBAM007.TSM (14 KB) - TINA-TI Spice Model
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시뮬레이션 모델

ADS62Pxx IBIS Model (Rev. A)

SLAC176A.ZIP (921 KB) - IBIS Model
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계산 툴

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

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PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 착수하기 (...)
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VQFN (RGC) 64 Ultra Librarian
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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