패키징 정보
| 패키지 | 핀 CFP (HKQ) | 8 |
| 작동 온도 범위(°C) -55 to 210 |
| 패키지 수량 | 캐리어 25 | TUBE |
SN65HVD1040-HT의 주요 특징
- Improved Drop-in Replacement for the TJA1040
- ±12 kV ESD Protection
- Low-Current Standby Mode with Bus Wake-up: 5 µA Typical
- Bus-Fault Protection of –27 V to 40 V
- Rugged Split-Pin Bus Stability
- Dominant Time-Out Function
- Thermal Shutdown Removed
- Power-Up/Down Glitch-Free Bus Inputs and Outputs
- High Input Impedance with Low VCC
- Monotonic Outputs During Power Cycling
- DeviceNet Vendor ID # 806
SN65HVD1040-HT에 대한 설명
The SN65HVD1040 meets or exceeds the specifications of the ISO 11898 standard for use in applications employing a Controller Area Network (CAN). As CAN transceivers, these devices provide differential transmit and receive capability for a CAN controller at signaling rates of up to 1 megabit per second (Mbps). The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
Designed for operation in especially harsh environments, the device features ±12 kV ESD protection on the bus and split pins, cross-wire, overvoltage and loss of ground protection from –27 to 40 V, a –12 V to 12 V common-mode range, and will withstand voltage transients from –200 V to 200 V according to ISO 7637.
The STB input (pin 8) selects between two different modes of operation; high-speed or low-power mode. The high-speed mode of operation is selected by connecting STB to ground.
If a high logic level is applied to the STB pin of the SN65HVD1040, the device enters a low-power bus-monitor standby mode. While the SN65HVD1040 is in the low-power bus-monitor standby mode, a dominant bit greater than 5 µs on the bus is passed by the bus-monitor circuit to the receiver output. The local protocol controller may then reactivate the device when it needs to transmit to the bus.
A dominant-time-out circuit in the SN65HVD1040 prevents the driver from blocking network communication during a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no rising edge is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then reset by the next rising edge on TXD.
The SPLIT output (pin 5) is available on the SN65HVD1040 as a VCC/2 common-mode bus voltage bias for a split-termination network.
The SN65HVD1040 is characterized for operation from –55°C to 210°C.