SN74AHCT139

Name: SN74AHCT139
Brand: TI
SKU: SN74AHCT139
Price: 0.106 USD

활성

듀얼 2라인-4라인 디코더/디멀티플렉서

지금 주문

데이터 시트

document-pdfAcrobat SN54AHCT139, SN74AHCT139 datasheet (Rev. M) (영어)

SN74AHCT139

활성

데이터 시트

지금 주문

제품 상세 정보

Technology family

AHCT

Number of channels

2

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Supply current (max) (µA)

20

Technology family

AHCT

Number of channels

2

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Supply current (max) (µA)

20

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

SSOP (DB)

16

48.36 mm² 6.2 x 7.8

TSSOP (PW)

16

32 mm² 5 x 6.4

TVSOP (DGV)

16

23.04 mm² 3.6 x 6.4

Inputs Are TTL-Voltage Compatible
Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Inputs Are TTL-Voltage Compatible
Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

The ’AHCT139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 4.5-V to 5.5-V V_CC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

The ’AHCT139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 4.5-V to 5.5-V V_CC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

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