SN74AUC1G126

활성

3상 출력을 지원하는 단일 0.8V~2.7V 고속 버퍼

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document-pdfAcrobat SN74AUC1G126 Single Bus Buffer Gate With Tri-state Output datasheet (Rev. L) (영어) PDF | HTML

SN74AUC1G126

활성

데이터 시트

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제품 상세 정보

Technology family

AUC

Number of channels

1

IOL (max) (mA)

9

Supply current (max) (µA)

10

IOH (max) (mA)

-9

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AUC

Number of channels

1

IOL (max) (mA)

9

Supply current (max) (µA)

10

IOH (max) (mA)

-9

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

DSBGA (YZP)

5

2.1875 mm² (— mm × — mm)

SOT-23 (DBV)

5

8.12 mm² (2.9 mm × 2.8 mm)

SOT-SC70 (DCK)

5

4.2 mm² (2 mm × 2.1 mm)

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Available in TI’s NanoFree™ Package
Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial Power Down Mode and Back Drive Protection
Sub-1 V Operable
Maximum t_pd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Maximum I_CC
±8-mA Output Drive at 1.8 V

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Available in TI’s NanoFree™ Package
Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial Power Down Mode and Back Drive Protection
Sub-1 V Operable
Maximum t_pd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Maximum I_CC
±8-mA Output Drive at 1.8 V

The SN74AUC1G126 bus buffer gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC1G126 device is a single line driver with a tri-state output. The output is disabled when the output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

NanoFree™ package technology is a major breakthrough in device packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, which prevents damaging current backflow through the device when it is powered down.

The SN74AUC1G126 bus buffer gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC1G126 device is a single line driver with a tri-state output. The output is disabled when the output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

NanoFree™ package technology is a major breakthrough in device packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, which prevents damaging current backflow through the device when it is powered down.

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