패키징 정보
| 패키지 | 핀 VQFN (RGE) | 24 |
| 작동 온도 범위(°C) -40 to 85 |
| 패키지 수량 | 캐리어 250 | SMALL T&R |
TLV320ADC3100의 주요 특징
- Stereo Audio ADC:
- 92-dBA Signal-to-Noise Ratio
- Supports ADC Sample Rates From 8 kHz to 96 kHz
- Flexible Digital Filtering With Programmable Coefficients and Built-In Processing
Blocks:
- Low-Latency IIR Filters for Voice
- Linear Phase FIR Filters for Audio
- Up to 5 Additional Programmable Bi-Quad Filters
- Programmable High-Pass Filter
- Four Audio Inputs With Configurable Automatic Gain Control (AGC):
- Programmable in Single-Ended or Fully Differential Configurations
- Optionally Tri-Stated for Easy Interoperability With Other Audio Devices
- Low Power Consumption and Extensive Modular Power Control:
- 6-mW Mono Record, 8-kHz
- 11-mW Stereo Record, 8-kHz
- 10-mW Mono Record, 48-kHz
- 17-mW Stereo Record, 48-kHz
- Programmable Microphone Bias
- Programmable PLL for Clock Generation
- I2C Control Bus
- Audio Serial Data Bus Supports I2S, Left- and Right-Justified, DSP, PCM, and TDM Modes
- Power Supplies:
- Analog: 2.7 V to 3.6 V
- Digital: Core: 1.65 V to 1.95 V,
I/O: 1.1 V–3.6 V
- Package: 4-mm × 4-mm, 24-Pin RGE (VQFN)
TLV320ADC3100에 대한 설명
The TLV320ADC3100 is a low-power, stereo audio analog-to-digital converter (ADC) supporting sampling rates from 8 kHz to 96 kHz with an integrated programmable-gain amplifier (PGA) providing up to 40-dB analog gain or automatic gain control (AGC). Front-end input coarse attenuation of 0 dB, –6 dB, or off, is also provided. The inputs are programmable in a combination of single-ended or fully differential configurations. Extensive register-based power control is available via an I2C interface, enabling mono or stereo recording. The TLV320ADC3100 integrates programable channel gain, digital volume control, a phase-locked loop (PLL), programmable biquad filters, and low latency filter modes. Pre-programmed built-in processing blocks (PRBs) that can be chosen based on the specific application needs, allows optimization of performance and power. Low power consumption coupled with its flexibility make the TLV320ADC3100 ideal for battery-powered portable equipment. The TLV320ADC3100 is form-factor and software compatible with the TLV320ADC3101.
The AGC programs to a wide range of attack (7 ms to 1.4 s) and decay (50 ms to 22.4 s) times. A programmable noise-gate function is included to avoid noise pumping. Low-latency interrupt identification register (IIR) filters optimized for voice and telephony are available, as well as linear-phase finite impulse response (FIR) filters optimized for audio. Programmable IIR filters are also available and can be used for sound equalization, or to remove noise components. The audio serial bus can be programmed to support I2S, left-justified, right-justified, digital signal processor (DSP), pulse code modulation (PCM), and time-division multiplexing (TDM) modes. The audio bus can be operated in either master or slave mode.
A programmable integrated PLL is included for flexible clock generation and provides support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, including the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks.