TMS320C6712D
- Low-Price/High-Performance Floating-Point Digital Signal Processor (DSP):
- TMS320C6712D
- Eight 32-Bit Instructions/Cycle
- 150-MHz Clock Rate
- 6.7-ns Instruction Cycle Time
- 900 MFLOPS
- Advanced Very Long Instruction Word (VLIW) C67x™ DSP Core
- Eight Highly Independent Functional Units:
- Four ALUs (Floating- and Fixed-Point)
- Two ALUs (Fixed-Point)
- Two Multipliers (Floating- and Fixed-Point)
- Load-Store Architecture With 32 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Eight Highly Independent Functional Units:
- Instruction Set Features
- Hardware Support for IEEE Single-Precision and Double-Precision Instructions
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
- L1/L2 Memory Architecture
- 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
- 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
- 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
- Device Configuration
- Boot Mode: 8- and 16-Bit ROM Boot
- Little Endian, Big Endian
- Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
- 16-Bit External Memory Interface (EMIF)
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- 256M-Byte Total Addressable External Memory Space
- Two Multichannel Buffered Serial Ports (McBSPs)
- Direct Interface to T1/E1, MVIP, SCSA Framers
- ST-Bus-Switching Compatible
- Up to 256 Channels Each
- AC97-Compatible
- Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
- Two 32-Bit General-Purpose Timers
- Flexible Software-Configurable PLL-Based Clock Generator Module
- A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins
- IEEE-1149.1 (JTAG
) Boundary-Scan-Compatible - 272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffix)
- CMOS Technology
- 0.13-µm/6-Level Copper Metal Process
- 3.3-V I/Os, 1.20
-V Internal
TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
Other trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26V designs.
TMS320C6000 and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Throughout the remainder of this document, the TMS320C6712D shall be referred to as its individual full device part number or abbreviated as C6712D or 12D.
The TMS320C67x™ DSP (including the TMS320C6712, TMS320C6712C, TMS320C6712D devices) are members of the floating-point DSP family in the TMS320C6000. DSP platform. The C6712, C6712C, and C6712D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.
With performance of up to 900 million floating-point operations per second (MFLOPS) at a clock rate of 150 MHz, the C6712D device is the lowest-cost DSP in the C6000™ DSP platform. The C6712D DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6712D can produce two MACs per cycle for a total of 300 MMACS.
The C6712D uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, and a glueless 16-bit external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The C6712D device also includes a dedicated general-purpose input/output (GPIO) peripheral module.
The C6712D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The C6712D has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.
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기술 자료
설계 및 개발
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모든 XDS 디버그 프로브는 ETB(임베디드 추적 버퍼)가 있는 모든 ARM 및 DSP 프로세서에서 코어와 시스템 트레이스를 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.
XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, TI 20핀 및 ARM (...)
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All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)
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Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)
CCSTUDIO — Code Composer Studio integrated development environment (IDE)
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C64X-DSPLIB — Download TMS320C64x DSP Library
TMS320C6000 DSPLIB(디지털 신호 프로세서 라이브러리)는 C 프로그래머를 위한 플랫폼에 최적화된 DSP 기능 라이브러리입니다. 여기에는 일반적으로 계산 집약적 실시간 애플리케이션에서 사용되는 C 호출 가능한 범용 신호 처리 루틴이 포함되어 있습니다. 이 루틴을 사용하면 상응하는 표준 ANSI C 언어 코드보다 더 높은 성능을 달성할 수 있습니다. DSPLIB는 즉시 사용할 수 있는 DSP 기능을 소스 코드와 함께 제공하여 애플리케이션 개발 시간을 크게 단축시킬 수 있습니다.
벤치마크 확인: DSP 코어 벤치마크
C67X-DSPLIB — Download TMS320C67x DSP Library
TMS320C6000 DSPLIB(디지털 신호 프로세서 라이브러리)는 C 프로그래머를 위한 플랫폼에 최적화된 DSP 기능 라이브러리입니다. 여기에는 일반적으로 계산 집약적 실시간 애플리케이션에서 사용되는 C 호출 가능한 범용 신호 처리 루틴이 포함되어 있습니다. 이 루틴을 사용하면 상응하는 표준 ANSI C 언어 코드보다 더 높은 성능을 달성할 수 있습니다. DSPLIB는 즉시 사용할 수 있는 DSP 기능을 소스 코드와 함께 제공하여 애플리케이션 개발 시간을 크게 단축시킬 수 있습니다.
벤치마크 확인: DSP 코어 벤치마크
C67X-MATHLIB — DSP Math Library for C67x Floating Point Devices
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| PBGA (GDP) | 272 | Ultra Librarian |
| BGA (ZDP) | 272 | Ultra Librarian |