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The SCAN921821 is a dual channel 18-bit serializer featuring signal conditioning, boundary SCAN, and at-speed BIST. Each serializer block transforms an 18-bit parallel LVCMOS/LVTTL data bus into a single Bus LVDS data stream with embedded clock. This single serial data stream with embedded clock simplifies PCB design and reduces PCB cost by narrowing data paths that in turn reduce PCB size and layers. The single serial data stream also reduces cable size, the number of connectors, and eliminates clock-to-data and data-to-data skew.
Each channel also has an 8-level selectable pre-emphasis feature that significantly extends performance over lossy interconnect. Each channel also has its own powerdown pin that saves power by reducing supply current when the channel is not being used.
The SCAN921821 also incorporates advanced testability features including IEEE 1149.1 and at-speed BIST PRBS pattern generation to facilitate verification of board and link integrity
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | SCAN921821 Dual 18-Bit Serializer w/Pre-emph, IEEE 1149.1 JTAG & At-Speed BIST datasheet (Rev. C) | Apr 15, 2013 | |
| Application note | External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A) | Apr 26, 2013 | ||
| Design guide | 18-bit SerDes Design Guide (DS92LV18, SCAN921821) | Mar 29, 2007 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| NFBGA (NZD) | 100 | Ultra Librarian |
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