TLK1002A is a single-chip dual signal conditioning transceiver.
This chip supports data rates from 1.0 Gbps up to 1.3 Gbps. An on-chip clock generation phase-locked loop (PLL) generates the required half-rate clock from an externally applied reference clock. This reference clock equals approximately one tenth of the data rate. It may be off frequency from both received data streams by up to ±200 ppm.
Both data paths are implemented identical. The implemented input buffers provide an input sensitivity of 400 mVp-p differential.
The data paths tolerate up to 0.606 UI total input jitter. Signal retiming is performed by means of phase-locked loop (PLL) circuits. The retimed output signals are fed to VML output buffers, which provide output amplitudes of typical 1600mVp-p differential across the external 2x50 
load.
TLK1002A only requires a single 1.8 V supply voltage. Robust design avoids the necessity of special off-chip supply filtering.
Advanced low power CMOS design leads to low power consumption.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | Dual Signal Conditioning Transceiver datasheet | Jun 28, 2005 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RGE) | 24 | Ultra Librarian |
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