ADC09QJ1300-Q1
- AEC-Q100 qualified for automotive applications:
- Temperature grade 1: –40°C to +125°C, TA
- ADC Core:
- Resolution: 9 Bit
- Maximum sampling rate: 1.3GSPS
- Non-interleaved architecture
- Internal dither reduces high-order harmonics
- Performance specifications (–1dBFS):
- SNR (100MHz): 53.5dBFS
- ENOB (100MHz): 8.5Bits
- SFDR (100MHz): 64dBc
- Noise floor (–20dBFS): –143dBFS
- Full-scale input voltage: 800mVPP-DIFF
- Full-power input bandwidth: 6GHz
- JESD204C Serial data interface:
- Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
- Maximum baud-rate: 17.16Gbps
- 64B/66B and 8B/10B encoding modes
- Subclass-1 support for deterministic latency
- Compatible with JESD204B receivers
- Optional internal sampling clock generation
- Internal PLL and VCO (7.2–8.2GHz)
- SYSREF Windowing eases synchronization
- Four clock outputs simplify system clocking
- Reference clocks for FPGA or adjacent ADC
- Reference clock for SerDes transceivers
- Timestamp input and output for pulsed systems
- Power consumption (1GSPS):
- Quad Channel: 450mW / channel
- Dual channel: 625mW / channel
- Single channel: 940mW
- Power supplies: 1.1V, 1.9V
ADC09xJ1300-Q1 is a family of quad, dual and single channel, 9-bit, 1.3 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300-Q1 ideally suited for light detection and ranging (LiDAR) systems. ADC09xJ1300-Q1 is qualified for automotive applications.
Full-power input bandwidth (-3dB) of 6GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4GHz.
A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC09xJ1300-Q1 Quad, Dual, Single Channel, 1.3GSPS, 9-bit Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. B) | PDF | HTML | 2024/10/22 |
設計與開發
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ADC09xJ800, ADC09xJ1300, ADC12xJ800 and ADC12xJ1600 IBIS-AMI Model (Rev. A)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。