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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC12DJ5200-EP

現行

具有雙通道 5.2 GSPS 或單通道 10.4 GSPS 的強化型產品 12 位元 ADC

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ADC12DJ5200-EP

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 7900 Features Ultra High Speed Rating HiRel Enhanced Product Peak-to-peak input voltage range (V) 0.825 Power consumption (typ) (mW) 4000 Architecture Folding Interpolating SNR (dB) 55.6 ENOB (bit) 8.8 SFDR (dB) 65 Operating temperature range (°C) -55 to 125 Input buffer Yes
Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 7900 Features Ultra High Speed Rating HiRel Enhanced Product Peak-to-peak input voltage range (V) 0.825 Power consumption (typ) (mW) 4000 Architecture Folding Interpolating SNR (dB) 55.6 ENOB (bit) 8.8 SFDR (dB) 65 Operating temperature range (°C) -55 to 125 Input buffer Yes
FCCSP (ALR) 144 100 mm² 10 x 10
  • High reliability enhanced product:
    • Controlled baseline: one assembly and test site, one fabrication site, extended product lifecycle, extended product-change notification and product traceability
  • ADC core:
    • 12-bit resolution
    • Up to 10.4 GSPS in single-channel mode
    • Up to 5.2 GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20 dBFS, VFS = 1 VPP-DIFF):
      • Dual-channel mode: –151.8 dBFS/Hz
      • Single-channel mode: –154.4 dBFS/Hz
    • ENOB (dual channel, FIN = 2.4 GHz): 8.6 Bits
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8 GHz
    • Usable input frequency range: > 10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Time stamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16 Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • 4x, 8x, 16x and 32x complex decimation
    • Four independent 32-Bit NCOs per DDC
  • Peak RF Input Power (Diff): +26.5 dBm (+ 27.5 dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 4 W
  • Power supplies: 1.1 V, 1.9 V
  • High reliability enhanced product:
    • Controlled baseline: one assembly and test site, one fabrication site, extended product lifecycle, extended product-change notification and product traceability
  • ADC core:
    • 12-bit resolution
    • Up to 10.4 GSPS in single-channel mode
    • Up to 5.2 GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20 dBFS, VFS = 1 VPP-DIFF):
      • Dual-channel mode: –151.8 dBFS/Hz
      • Single-channel mode: –154.4 dBFS/Hz
    • ENOB (dual channel, FIN = 2.4 GHz): 8.6 Bits
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8 GHz
    • Usable input frequency range: > 10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19-fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Time stamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16 Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Optional digital down-converters (DDC):
    • 4x, 8x, 16x and 32x complex decimation
    • Four independent 32-Bit NCOs per DDC
  • Peak RF Input Power (Diff): +26.5 dBm (+ 27.5 dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 4 W
  • Power supplies: 1.1 V, 1.9 V

The ADC12DJ5200-EP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. ADC12DJ5200-EP can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. Support of a useable input frequency range of up to 10 GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ5200-EP uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters (DDCs) are available to provide digital conversion to base-band and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.

The ADC12DJ5200-EP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. ADC12DJ5200-EP can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. Support of a useable input frequency range of up to 10 GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ5200-EP uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16 Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multichannel applications. Optional digital down converters (DDCs) are available to provide digital conversion to base-band and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
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* Data sheet ADC12DJ5200-EP 10.4-GSPS Single-Channel or 5.2-GSPS Dual-Channel, 12-bit,RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. C) PDF | HTML 2023年 3月 11日

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開發板

ADC12DJ5200RFEVM — ADC12DJ5200RF 射頻取樣 12 位元雙 5.2-GSPS 或單 10.4-GSPS ADC 評估模組

ADC12DJ5200RF 評估模組 (EVM) 可供評估裝置 ADC12DJ5200RF 的評估。ADC12DJ5200RF 是低功耗、12 位元、雙 5.2-GSPS/單 10.4-GSPS、具有緩衝類比輸入的射頻取樣類比轉數位轉換器 (ADC)、具可編程 NCO 和降取設定 (包括未降取的 12 位元和 8 位元 ADC 輸出) 和具有 JESD204B/C 介面的整合式數位降壓轉換器。該 EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。

EVM 隨附 LMX2582 時鐘合成器和 LMK04828 JESD204B/C 時鐘產生器，可配置為提供適用於完整 (...)

使用指南: PDF | HTML
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ADC12DJ5200RF IBIS and IBIS-AMI Model (Rev. A)

SLVMD65A.ZIP (49879 KB) - IBIS-AMI Model
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模擬型號

ADC12DJ5200RF S-Parameter Model

SLVMDX5.ZIP (1563 KB) - S-Parameter Model
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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