ADC32RF72
- 16-bit, dual channel 1.5GSPS ADC
- Noise spectral density: -163.7dBFS/Hz
- Thermal Noise: 75.6dBFS
- Noise figure: 14.4dB
- Single core (non-interleaved) ADC architecture
- Aperture jitter: 40fs
- Buffered analog inputs
- Input fullscale: 1.44Vpp (4.1dBm)
- Full power input bandwidth (-3dB): 1.8GHz
- Ultra-low close-in residual phase noise:
- −140dBc/Hz at 10kHz offset at 1GHz
- Spectral performance (fIN = 1GHz, -1dBFS):
- SNRflat: 72.1dBFS
- HD2,3: 68dBc
- Non HD2,3: 93dBFS
- 192-tap/ch programmable FIR equalizer filter
- 12-bit Fractional delay filter
- Digital down-converters (DDCs)
- Up to 8 DDC
- Complex output: /2, /3, /4, /5 to /32768 decimation
- 48-bit NCO phase coherent frequency hopping
- Fast frequency hopping: < 1µs
- JESD204B/C serial data interface
- Maximum lane rate: 24.75Gbps
- Code error rate (CER): 1E-15 errors/sample
- Power consumption: 1.5W/channel (1.5GSPS)
The ADC32RF72 is a 16-bit, 1.5GSPS (non-interleaved), dual channel analog to digital converter (ADC). The device is designed for the highest signal-to-noise ratio (SNR) and delivers a noise spectral density of −163.7dBFS/Hz. Using internal averaging modes, the NSD can be improved to as low as -166.2dBFS/Hz. The buffered analog inputs support a programmable internal termination impedance of 50, 100, 200Ω with a full power input bandwidth of 1.8GHz (−3dB). The device lets the user select one input from IN1/2/3 in addition to IN0.
The device includes several digital processing features such as a 192-tap/ch programmable FIR filter for equalization, a 12-bit fractional delay filter as well as multiple digital down converters (DDCs). There are eight DDCs supporting decimation factors of /2, /3 and /5 up to /32768. The 48-bit NCOs support phase coherent frequency hopping.
The ADC32RF72 supports the JESD204B/C serial data interface with interface rates up to 24.75Gbps. The power efficient ADC architecture consumes 1.5W/ch at 1.5GSPS and provides power scaling with lower sampling rates.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC32RF72 Dual Channel 1.5GSPS 16-bit RF Sampling ADC datasheet | PDF | HTML | 2025/11/20 | ||
| 類比設計期刊 | 高速轉換器奈奎斯特(Nyquist)孔周圍取樣 | PDF | HTML | Download English Version | PDF | HTML | 2025/5/23 | |
| 應用說明 | Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends | PDF | HTML | 2025/3/28 | |||
| 應用說明 | Evaluating High-Speed, RF ADC Converter Front-end Architectures | PDF | HTML | 2025/3/26 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
ADC34RF72EVM — ADC3xRF72 評估模組
ADC3XRF7X-API-APPSW — Software development package for ADC3XRF7X device family
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (ANH) | 289 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。