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ADS117L11

現行

配備輸入和參考緩衝器的 16 位元、400-kSPS、低功耗、寬頻 Delta-Sigma ADC

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產品規格表

ADS117L11

現行
產品規格表 立即訂購

產品詳細資料

Resolution (Bits) 16 Sample rate (max) (ksps) 1000 Number of input channels 1 Interface type SPI Architecture Delta-Sigma Input type Differential, Pseudo-Differential, Single-ended Rating Catalog TI functional safety category Functional Safety-Capable Reference mode External Input voltage range (max) (V) 5 Input voltage range (min) (V) 0 Features 50/60 Hz Rejection, Daisy-Chainable, Oscillator, Small Size, Wideband Operating temperature range (°C) -40 to 125 Power consumption (typ) (mW) 3.3 Analog supply voltage (min) (V) 2.85 Analog supply voltage (max) (V) 5.5 SNR (dB) 97.2 Digital supply (min) (V) 1.65 Digital supply (max) (V) 5.5
Resolution (Bits) 16 Sample rate (max) (ksps) 1000 Number of input channels 1 Interface type SPI Architecture Delta-Sigma Input type Differential, Pseudo-Differential, Single-ended Rating Catalog TI functional safety category Functional Safety-Capable Reference mode External Input voltage range (max) (V) 5 Input voltage range (min) (V) 0 Features 50/60 Hz Rejection, Daisy-Chainable, Oscillator, Small Size, Wideband Operating temperature range (°C) -40 to 125 Power consumption (typ) (mW) 3.3 Analog supply voltage (min) (V) 2.85 Analog supply voltage (max) (V) 5.5 SNR (dB) 97.2 Digital supply (min) (V) 1.65 Digital supply (max) (V) 5.5
WQFN (RUK) 20 9 mm² (3 mm × 3 mm)
  • Programmable data rate:
    • Up to 400 kSPS (wideband filter)
    • Up to 1.067 MSPS (low-latency filter)
  • Selectable digital filter:
    • Wideband or low-latency
  • AC accuracy with dc precision:
    • Dynamic range: 97.5 dB (200 kSPS), typical
    • THD: –110 dB, typical
    • INL: 0.5 LSB, typical
    • Offset drift: 50 nV/°C, typical
    • Gain drift: 0.6 ppm/°C, typical
  • Power-scalable architecture:
    • High-speed mode: 400 kSPS, 18.6 mW
    • Low-speed mode: 50 kSPS, 3.3 mW
  • Input and reference precharge buffers
  • Internal or external clock
  • Functional Safety-Capable
  • Programmable data rate:
    • Up to 400 kSPS (wideband filter)
    • Up to 1.067 MSPS (low-latency filter)
  • Selectable digital filter:
    • Wideband or low-latency
  • AC accuracy with dc precision:
    • Dynamic range: 97.5 dB (200 kSPS), typical
    • THD: –110 dB, typical
    • INL: 0.5 LSB, typical
    • Offset drift: 50 nV/°C, typical
    • Gain drift: 0.6 ppm/°C, typical
  • Power-scalable architecture:
    • High-speed mode: 400 kSPS, 18.6 mW
    • Low-speed mode: 50 kSPS, 3.3 mW
  • Input and reference precharge buffers
  • Internal or external clock
  • Functional Safety-Capable

The ADS117L11 is a 16-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) with data rates up to 400 kSPS using the wideband filter and up to 1067 kSPS using the low-latency filter. The device offers an excellent combination of ac performance and dc precision with low power consumption (18.6 mW in high-speed mode).

The device integrates input and reference buffers to reduce signal loading. The low-drift modulator achieves excellent dc precision with low in-band noise for outstanding ac performance. The power-scalable architecture provides two speed modes to optimize data rate, resolution, and power consumption.

The digital filter is configurable for wideband or low-latency operation, optimizing ac performance or data throughput for dc signals, all in one device.

The serial interface features daisy-chain capability to reduce the SPI I/O over an isolation barrier. Input and output data and register settings are validated by a cyclic-redundancy check (CRC) feature to enhance operational reliability.

The small 3-mm × 3-mm WQFN package is designed for limited space applications. The device is fully specified for operation over the –40°C to +125°C temperature range.

The ADS117L11 is a 16-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) with data rates up to 400 kSPS using the wideband filter and up to 1067 kSPS using the low-latency filter. The device offers an excellent combination of ac performance and dc precision with low power consumption (18.6 mW in high-speed mode).

The device integrates input and reference buffers to reduce signal loading. The low-drift modulator achieves excellent dc precision with low in-band noise for outstanding ac performance. The power-scalable architecture provides two speed modes to optimize data rate, resolution, and power consumption.

The digital filter is configurable for wideband or low-latency operation, optimizing ac performance or data throughput for dc signals, all in one device.

The serial interface features daisy-chain capability to reduce the SPI I/O over an isolation barrier. Input and output data and register settings are validated by a cyclic-redundancy check (CRC) feature to enhance operational reliability.

The small 3-mm × 3-mm WQFN package is designed for limited space applications. The device is fully specified for operation over the –40°C to +125°C temperature range.
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ADS127L11 現行 具有易於驅動的輸入和寬頻或低延遲濾波器的 24 位元 400 kSPS Delta-Sigma ADC Increased performance, 24-bit

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 ADS117L11 400-kSPS, Wide-Bandwidth, 16-Bit, Delta-Sigma ADC datasheet (Rev. A) PDF | HTML 2022/10/3
應用說明 Design Considerations for Multiple Wide Bandwidth Delta- Sigma ADCs in Simultaneous-Sampling Systems (Rev. A) PDF | HTML 2025/12/29
功能安全資訊 ADS1x7Lx1x Functional Safety FIT Rate, FMD and Pin FMA (Rev. C) PDF | HTML 2024/9/26
應用說明 Digital Filter Types in Delta-Sigma ADCs (Rev. A) PDF | HTML 2023/3/29
設計指南 Four-Channel Synchronous IEPE Vibration Sensor Interface Reference Design PDF | HTML 2022/11/28
Application brief THP210 and ADS127L11 Performance PDF | HTML 2022/3/28

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ADS127L11EVM-PDK — ADS127L11 評估模組，適用於具有易於驅動的輸入和寬頻或低延遲濾波器的 ADC

ADS127L11 評估模組 (EVM) 性能展示套件 (PDK)，這是一款用於評估 ADS127L11 的平台，是 24 位元、高速寬頻 delta-sigma (ΔΣ) 類比轉數位轉換器 (ADC) 的平台。

PDK 內含 ADS127L11 評估板、精密主機介面 (PHI) 控制器電路板，以及隨附的電腦軟體，可讓使用者透過通用序列匯流排 (USB) 與 ADC 通訊、擷取資料，以及執行資料分析。

使用指南: PDF | HTML
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計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。

除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。

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設計工具

ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.

The ADC-TO-VREF-SELECT tool enables the pairing of TI analog-to-digital converters (ADCs) and series voltage references. Users can select an ADC device and the desired reference voltage, and the tool will list up to two voltage reference recommendations.
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WQFN (RUK) 20 Ultra Librarian
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