ADS4142
- Ultra-Low Power With 1.8-V Single Supply:
- 103-mW Total Power at 65 MSPS
- 153-mW Total Power at 125 MSPS
- High Dynamic
Performance:
- SNR: 72.2 dBFS at 170 MHz
- SFDR: 81 dBc at 170 MHz
- Dynamic Power Scaling With Sample Rate
- Idle Channel SNR 74.8 dBFS (ADS414x)
- Output
Interface:
- Double Data Rate (DDR) LVDS With Programmable Swing and
Strength:
- Standard Swing: 350 mV
- Low Swing: 200 mV
- Default Strength: 100-Ω Termination
- 2x Strength: 50-Ω Termination
- 1.8-V Parallel CMOS Interface Also Supported
- Double Data Rate (DDR) LVDS With Programmable Swing and
Strength:
- Programmable Gain up to 6 dB for SNR, SFDR Trade-Off
- DC Offset Correction
- Supports Low Input Clock Amplitude Down to 200 mVPP
The ADS412x and ADS414x devices are lower-sampling speed variants in the ADS41xx family of analog-to-digital converters (ADCs). These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8-V supply. The devices are well-suited for multi-carrier, wide bandwidth communications applications.
The ADS412x and ADS414x devices have fine gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. They include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled down power with no loss in performance.
The ADS412x and ADS414x devices are available in a compact VQFN-48 package and are specified over the industrial temperature range (–40°C to +85°C).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADS41xx 14-, 12-Bit, 65-, 125-MSPS, Ultra-Low-Power ADC datasheet (Rev. C) | PDF | HTML | 2017/6/8 | ||
| * | 使用指南 | Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) | 2012/7/10 | |||
| 應用說明 | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015/5/22 | ||||
| 應用說明 | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013/7/19 | ||||
| 應用說明 | Band-Pass Filter Design Techniques for High-Speed ADCs | 2012/2/27 | ||||
| 應用說明 | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010/9/10 | ||||
| 應用說明 | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009/4/28 | ||||
| 應用說明 | CDCE62005 as Clock Solution for High-Speed ADCs | 2008/9/4 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 | ||||
| 應用說明 | QFN Layout Guidelines | 2006/7/28 |
設計與開發
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使用者可以向 DATACONVERTERPRO-SW 提供自訂模式，以載入到 TI DAC。支援從 (...)
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類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。