ADS42LB49

現行

雙通道、14 位元、250-MSPS 類比轉數位轉換器 (ADC)

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產品規格表

document-pdfAcrobat ADS42LBx9 14- and 16-Bit, 250-MSPS, Analog-to-Digital Converters datasheet (Rev. F) (英文) PDF | HTML

使用指南

document-pdfAcrobat
Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) (英文)

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ADC3648

現行

具有 LVDS 介面和高達 32768x 降取的 14 位元、雙通道、250MSPS ADC Lower power

ADS42LB49

現行

立即訂購

產品詳細資料

Sample rate (max) (Msps)

250

Resolution (Bits)

14

Number of input channels

2

Interface type

DDR LVDS, QDR LVDS

Analog input BW (MHz)

900

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2.5

Power consumption (typ) (mW)

1640

Architecture

Pipeline

SNR (dB)

74.9

ENOB (Bits)

11.93

SFDR (dB)

90

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

250

Resolution (Bits)

14

Number of input channels

2

Interface type

DDR LVDS, QDR LVDS

Analog input BW (MHz)

900

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2.5

Power consumption (typ) (mW)

1640

Architecture

Pipeline

SNR (dB)

74.9

ENOB (Bits)

11.93

SFDR (dB)

90

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

VQFN (RGC)

64

81 mm² (9 mm × 9 mm)

Dual Channel
14- and 16-Bit Resolution
Maximum Clock Rate: 250 MSPS
Analog Input Buffer with High Impedance Input
Flexible Input Clock Buffer with
Divide-by-1, -2, and -4
2-V_PP and 2.5-V_PP Differential Full-Scale Input (SPI-Programmable)
DDR or QDR LVDS Interface
64-Pin VQFN Package (9-mm × 9-mm)
Power Dissipation: 820 mW/ch
Aperture Jitter: 85 f_S
Internal Dither
Channel Isolation: 100 dB
Performance at f_IN = 170 MHz at 2 V_PP, –1 dBFS
- SNR: 73.2 dBFS
- SFDR:
  - 87 dBc (HD2 and HD3)
  - 100 dBc (Non HD2 and HD3)
Performance at f_IN = 170 MHz:
2.5 V_PP, –1 dBFS
- SNR: 74.9 dBFS
- SFDR:
  - 85 dBc (HD2 and HD3)
  - 97 dBc (Non HD2 and HD3)

Dual Channel
14- and 16-Bit Resolution
Maximum Clock Rate: 250 MSPS
Analog Input Buffer with High Impedance Input
Flexible Input Clock Buffer with
Divide-by-1, -2, and -4
2-V_PP and 2.5-V_PP Differential Full-Scale Input (SPI-Programmable)
DDR or QDR LVDS Interface
64-Pin VQFN Package (9-mm × 9-mm)
Power Dissipation: 820 mW/ch
Aperture Jitter: 85 f_S
Internal Dither
Channel Isolation: 100 dB
Performance at f_IN = 170 MHz at 2 V_PP, –1 dBFS
- SNR: 73.2 dBFS
- SFDR:
  - 87 dBc (HD2 and HD3)
  - 100 dBc (Non HD2 and HD3)
Performance at f_IN = 170 MHz:
2.5 V_PP, –1 dBFS
- SNR: 74.9 dBFS
- SFDR:
  - 85 dBc (HD2 and HD3)
  - 97 dBc (Non HD2 and HD3)

The ADS42LB49 and ADS42LB69 are a family of high-linearity, dual-channel, 14- and 16-bit,
250-MSPS, analog-to-digital converters (ADCs) supporting DDR and QDR LVDS output interfaces. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS42LBx9 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with low-power consumption.

For all available packages, see the orderable addendum at the end of the datasheet.

The ADS42LB49 and ADS42LB69 are a family of high-linearity, dual-channel, 14- and 16-bit,
250-MSPS, analog-to-digital converters (ADCs) supporting DDR and QDR LVDS output interfaces. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS42LBx9 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with low-power consumption.

For all available packages, see the orderable addendum at the end of the datasheet.

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重要文件	類型	標題	格式選項
*	資料表	ADS42LBx9 14- and 16-Bit, 250-MSPS, Analog-to-Digital Converters datasheet (Rev. F)	PDF \| HTML	2016/5/2
*	使用指南	Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide)		2012/7/10
	應用說明	Correcting the Low-Frequency Response of the ADS42LBxx, ADS42JBxx for Time-Domai		2016/5/2
	應用說明	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)		2015/5/22
	應用說明	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)		2013/7/19

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ADS42LB49EVM — ADS42LB49 雙通道、14 位元 250-MSPS 類比轉數位轉換器評估模組

The ADS42LB49EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS42LB49. The ADS42LB49 is a low power, 14-bit, 250-MSPS analog to digital converter (ADC) with a buffered analog input and LVDS outputs. The EVM has transformer coupled analog and clock inputs to (...)

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Abaco FMC168 是一款數位轉換器，搭載八個具有 16 位元解析度和每通道 250-MSPS 取樣率的類比數位轉換器 (ADC) 通道。FMC168 具備彈性的時脈產生與分配機制，可透過與載卡的序列通訊，控制取樣頻率和類比輸入增益。

FMC168 之設計是以四個德州儀器 ADS42LB69 雙通道、16 位元、250-MSPS 低電壓差分訊號 (LVDS) ADC 為基礎。

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DATACONVERTERPRO-SW — 高速資料轉換器 Pro GUI 安裝程式，v5.31

這款高速資料轉換器專業 GUI 是一款 PC（與 Windows® XP/7/10 相容）程式，旨在協助評估大多數 TI 高速資料轉換器 [類比轉數位轉換器 (ADC) 和數位轉類比轉換器 (DAC)] 和類比前端 (AFE) 平台。DATACONVERTERPRO-SW 旨在支援整個 TSW14xxx 系列資料擷取和模式產生卡，為時域和頻域中的資料轉換器分析提供強大且快速的解決方案，並支援單音、多音和調變訊號。此 GUI 也與 TI 模式產生 GUI 相容，可快速合成單音、多音和調變訊號。

使用者可以向 DATACONVERTERPRO-SW 提供自訂模式，以載入到 TI DAC。支援從 (...)

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