ADS61JB46

現行

14 位元 160-MSPS 類比轉數位轉換器 (ADC)

立即訂購

產品規格表

document-pdfAcrobat 14-Bit, Input-Buffered, 160-MSPS, Analog-to-Digital Converter with JESD204A Outp datasheet (Rev. B) (英文)

ADS61JB46

現行

立即訂購

產品詳細資料

Sample rate (max) (Msps)

160

Resolution (Bits)

14

Number of input channels

1

Interface type

JESD204A

Analog input BW (MHz)

480

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

583

Architecture

Pipeline

SNR (dB)

75

ENOB (Bits)

11.7

SFDR (dB)

77

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

160

Resolution (Bits)

14

Number of input channels

1

Interface type

JESD204A

Analog input BW (MHz)

480

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

583

Architecture

Pipeline

SNR (dB)

75

ENOB (Bits)

11.7

SFDR (dB)

77

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

VQFN (RHA)

40

36 mm² (6 mm × 6 mm)

Output Interface:
- Single-Lane and Dual-Lane Interfaces
- Maximum Data Rate: 3.125 Gbps
- Meets JEDEC JESD204A Specification
- CML Outputs with Current Programmable from 2 mA to 32 mA
Power Dissipation:
- 583 mW at 160 MSPS in Dual-Lane Mode
- Power Scales Down with Clock Rate
Input Interface: Buffered Analog Inputs
SNR at 185-MHz IF: –72.7 dBFS
Analog Input Dynamic Range: 2 V_PP
Reference Support:
External and Internal (Trimmed)
Supply:
- Analog and Digital: 1.8 V
- Input Buffer: 3.3 V
Programmable Digital Gain: 0 dB to 6 dB
Output: Straight Offset Binary or
Twos Complement
Package: 6-mm × 6-mm QFN-40

Output Interface:
- Single-Lane and Dual-Lane Interfaces
- Maximum Data Rate: 3.125 Gbps
- Meets JEDEC JESD204A Specification
- CML Outputs with Current Programmable from 2 mA to 32 mA
Power Dissipation:
- 583 mW at 160 MSPS in Dual-Lane Mode
- Power Scales Down with Clock Rate
Input Interface: Buffered Analog Inputs
SNR at 185-MHz IF: –72.7 dBFS
Analog Input Dynamic Range: 2 V_PP
Reference Support:
External and Internal (Trimmed)
Supply:
- Analog and Digital: 1.8 V
- Input Buffer: 3.3 V
Programmable Digital Gain: 0 dB to 6 dB
Output: Straight Offset Binary or
Twos Complement
Package: 6-mm × 6-mm QFN-40

The ADS61JB46 is a high-performance, low-power, single-channel, analog-to-digital converter with an integrated JESD204A output interface. Available in a 6-mm × 6-mm QFN package, with both single-lane and dual-lane output modes, the device offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per the IEEE standard 802.3-2002 part 3, clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample-and-hold switches and higher and more consistent input impedance.

The device is specified over the industrial temperature range (–40°C to +85°C).

The ADS61JB46 is a high-performance, low-power, single-channel, analog-to-digital converter with an integrated JESD204A output interface. Available in a 6-mm × 6-mm QFN package, with both single-lane and dual-lane output modes, the device offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per the IEEE standard 802.3-2002 part 3, clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample-and-hold switches and higher and more consistent input impedance.

The device is specified over the industrial temperature range (–40°C to +85°C).

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重要文件	類型	標題	格式選項	下載最新的英文版本		日期
*	資料表	14-Bit, Input-Buffered, 160-MSPS, Analog-to-Digital Converter with JESD204A Outp datasheet (Rev. B)			2013/10/4

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