產品詳細資料

Resolution (Bits) 16 Sample rate (max) (ksps) 250 Number of input channels 6 Interface type Byte-Wide, Parallel Architecture SAR Input type Pseudo-Differential Multichannel configuration Simultaneous Sampling Rating Catalog Reference mode External, Internal Input voltage range (max) (V) 2.6 Input voltage range (min) (V) 0 Operating temperature range (°C) -40 to 85 Power consumption (typ) (mW) 190 Analog supply voltage (min) (V) 4.75 Analog supply voltage (max) (V) 5.25 SNR (dB) 88 Digital supply (min) (V) 2.7 Digital supply (max) (V) 5.5
Resolution (Bits) 16 Sample rate (max) (ksps) 250 Number of input channels 6 Interface type Byte-Wide, Parallel Architecture SAR Input type Pseudo-Differential Multichannel configuration Simultaneous Sampling Rating Catalog Reference mode External, Internal Input voltage range (max) (V) 2.6 Input voltage range (min) (V) 0 Operating temperature range (°C) -40 to 85 Power consumption (typ) (mW) 190 Analog supply voltage (min) (V) 4.75 Analog supply voltage (max) (V) 5.25 SNR (dB) 88 Digital supply (min) (V) 2.7 Digital supply (max) (V) 5.5
TQFP (PAG) 64 144 mm² (12 mm × 12 mm)
  • Six Input Channels
  • Fully Differential Inputs
  • Six Independent 16-Bit ADCs
  • 4µs Total Throughput per Channel
  • Low Power:
    200mW in Normal Mode
    5mW in Nap Mode
    50µW in Power-Down Mode
  • TQFP-64 Package Package
  • APPLICATIONS
    • Motor Control
    • Multi-Axis Positioning Systems
    • 3-Phase Power Control

All trademarks are the property of their respective owners.

  • Six Input Channels
  • Fully Differential Inputs
  • Six Independent 16-Bit ADCs
  • 4µs Total Throughput per Channel
  • Low Power:
    200mW in Normal Mode
    5mW in Nap Mode
    50µW in Power-Down Mode
  • TQFP-64 Package Package
  • APPLICATIONS
    • Motor Control
    • Multi-Axis Positioning Systems
    • 3-Phase Power Control

All trademarks are the property of their respective owners.

The ADS8365 includes six, 16-bit, 250kSPS analog-to-digital converters (ADCs) with six fully differential input channels grouped into three pairs for high-speed simultaneous signal acquisition. Inputs to the sample-and-hold amplifiers are fully differential and are maintained differential to the input of the ADC. This architecture provides excellent common-mode rejection of 80dB at 50kHz, which is important in high-noise environments.

The ADS8365 offers a flexible, high-speed parallel interface with a direct address mode, a cycle, and a FIFO mode. The output data for each channel is available as a 16-bit word.

The ADS8365 includes six, 16-bit, 250kSPS analog-to-digital converters (ADCs) with six fully differential input channels grouped into three pairs for high-speed simultaneous signal acquisition. Inputs to the sample-and-hold amplifiers are fully differential and are maintained differential to the input of the ADC. This architecture provides excellent common-mode rejection of 80dB at 50kHz, which is important in high-noise environments.

The ADS8365 offers a flexible, high-speed parallel interface with a direct address mode, a cycle, and a FIFO mode. The output data for each channel is available as a 16-bit word.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 16-Bit, 250kSPS 6-Channel Simultaneous Sampling SAR Analog-to-Digital Converters datasheet (Rev. C) 2008/3/27
白皮書 Voltage-reference impact on total harmonic distortion 2016/8/1
電子書 Best of Baker's Best: Precision Data Converters -- SAR ADCs 2015/5/21
應用說明 Determining Minimum Acquisition Times for SAR ADCs, part 2 2011/3/17
應用說明 Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) 2010/11/10
更多文件說明 ADS8365EVM Readme Page Thank You Letter (Rev. A) 2006/12/5

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開發板

ADS8365M-EVM — ADS8365M 評估模組

The ADS8365M-EVM is designed for the prototyping and evaluation of the ADS8365 analog-to-digital converter (ADC). This high-resolution, 16 bit, parallel analog-to-digital, 250 kHz, SAR device, can be configured as a single or fully differential, pseudo-bipolar input. The EVM uses a (...)

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ADS8365 IBIS Model

SBAM147.ZIP (51 KB) - IBIS 模型
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計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面,列出各種常見計算,從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。

除了作為獨立工具使用外,此計算機還與類比工程師口袋參考中描述的概念相得益彰。

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JITTER-SNR-CALC — Jitter and SNR calculator

JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.

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設計工具

ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.

The ADC-TO-VREF-SELECT tool enables the pairing of TI analog-to-digital converters (ADCs) and series voltage references. Users can select an ADC device and the desired reference voltage, and the tool will list up to two voltage reference recommendations.
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TQFP (PAG) 64 Ultra Librarian

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