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THS4521

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極低功耗軌至軌輸出全差動放大器

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THS4551 現行 低雜訊、精密、150MHz、全差分放大器 Wider bandwidth (BW) (135 MHz), lower noise (3.3 nV/√Hz) and higher precision (0.175 mV)

THS4521

現行
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產品詳細資料

Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.5 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.5 BW at Acl (MHz) 145 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 490 Architecture Bipolar, Fully Differential ADC Driver Vn at flatband (typ) (nV√Hz) 4.6 Iq per channel (typ) (mA) 1.14 Rail-to-rail In to V-, Out Vos (offset voltage at 25°C) (max) (mV) 2 Operating temperature range (°C) -40 to 85 Iout (typ) (mA) 55 2nd harmonic (dBc) 133 3rd harmonic (dBc) 141 Frequency of harmonic distortion measurement (MHz) 0.001 GBW (typ) (MHz) 95 Input bias current (max) (pA) 900000 Features Shutdown CMRR (typ) (dB) 102 Rating Catalog
Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.5 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.5 BW at Acl (MHz) 145 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 490 Architecture Bipolar, Fully Differential ADC Driver Vn at flatband (typ) (nV√Hz) 4.6 Iq per channel (typ) (mA) 1.14 Rail-to-rail In to V-, Out Vos (offset voltage at 25°C) (max) (mV) 2 Operating temperature range (°C) -40 to 85 Iout (typ) (mA) 55 2nd harmonic (dBc) 133 3rd harmonic (dBc) 141 Frequency of harmonic distortion measurement (MHz) 0.001 GBW (typ) (MHz) 95 Input bias current (max) (pA) 900000 Features Shutdown CMRR (typ) (dB) 102 Rating Catalog
SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm) VSSOP (DGK) 8 14.7 mm² (3 mm × 4.9 mm)
  • Fully Differential Architecture
  • Bandwidth: 145 MHz (AV = 1 V/V)
  • Slew Rate: 490 V/µs
  • HD2: –133 dBc at 10 kHz (1 VRMS,
    RL = 1 kΩ)
  • HD3: –141 dBc at 10 kHz (1 VRMS,
    RL = 1 kΩ)
  • Input Voltage Noise: 4.6 nV/√Hz
    (f = 100 kHz)
  • THD+N: –112dBc (0.00025%) at
    1 kHz (22-kHz BW, G = 1, 5 VPP)
  • Open-Loop Gain: 119 dB (DC)
  • NRI–Negative Rail Input
  • RRO–Rail-to-Rail Output
  • Output Common-Mode Control
    (with Low Offset)
  • Power Supply:
    • Voltage: +2.5 V (±1.25 V) to
      +5.5 V (±2.75 V)
    • Current: 1.14 mA/ch
  • Power-Down Capability: 20 µA (typical)
  • Fully Differential Architecture
  • Bandwidth: 145 MHz (AV = 1 V/V)
  • Slew Rate: 490 V/µs
  • HD2: –133 dBc at 10 kHz (1 VRMS,
    RL = 1 kΩ)
  • HD3: –141 dBc at 10 kHz (1 VRMS,
    RL = 1 kΩ)
  • Input Voltage Noise: 4.6 nV/√Hz
    (f = 100 kHz)
  • THD+N: –112dBc (0.00025%) at
    1 kHz (22-kHz BW, G = 1, 5 VPP)
  • Open-Loop Gain: 119 dB (DC)
  • NRI–Negative Rail Input
  • RRO–Rail-to-Rail Output
  • Output Common-Mode Control
    (with Low Offset)
  • Power Supply:
    • Voltage: +2.5 V (±1.25 V) to
      +5.5 V (±2.75 V)
    • Current: 1.14 mA/ch
  • Power-Down Capability: 20 µA (typical)

The THS4521, THS4522, and THS4524 family of devices are very low-power, fully differential amplifiers with rail-to-rail output and an input common-mode range that includes the negative rail. These amplifiers are designed for low-power data acquisition systems and high-density applications where power dissipation is a critical parameter, and provide exceptional performance in audio applications.

The family includes single FDA (THS4521), dual FDA (THS4522), and quad FDA (THS4524) versions.

These fully differential amplifiers feature accurate output common-mode control that allows for dc-coupling when driving analog-to-digital converters (ADCs). This control, coupled with an input common-mode range below the negative rail as well as rail-to-rail output, allows for easy interfacing between single-ended, ground-referenced signal sources. Additionally, these devices are ideally suited for driving both successive-approximation register (SAR) and delta-sigma (ΔΣ) ADCs using only a single +2.5V to +5V and ground power supply.

The THS4521, THS4522, and THS4524 family of fully differential amplifiers is characterized for operation over the full industrial temperature range from –40°C to +85°C.

The THS4521, THS4522, and THS4524 family of devices are very low-power, fully differential amplifiers with rail-to-rail output and an input common-mode range that includes the negative rail. These amplifiers are designed for low-power data acquisition systems and high-density applications where power dissipation is a critical parameter, and provide exceptional performance in audio applications.

The family includes single FDA (THS4521), dual FDA (THS4522), and quad FDA (THS4524) versions.

These fully differential amplifiers feature accurate output common-mode control that allows for dc-coupling when driving analog-to-digital converters (ADCs). This control, coupled with an input common-mode range below the negative rail as well as rail-to-rail output, allows for easy interfacing between single-ended, ground-referenced signal sources. Additionally, these devices are ideally suited for driving both successive-approximation register (SAR) and delta-sigma (ΔΣ) ADCs using only a single +2.5V to +5V and ground power supply.

The THS4521, THS4522, and THS4524 family of fully differential amplifiers is characterized for operation over the full industrial temperature range from –40°C to +85°C.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 THS452x Very Low Power, Negative Rail Input, Rail-To-Rail Output, Fully Differential Amplifier datasheet (Rev. H) PDF | HTML 2015/6/18
Application brief Why Use an FDA to Drive an ADC? PDF | HTML 2026/1/8
Application brief Active Filter Design for Differential ADCs (Rev. A) PDF | HTML 2025/10/8
Circuit design High-speed overcurrent detection circuit (Rev. B) PDF | HTML 2024/10/2
Circuit design Single-ended input to differential output circuit using a fully-differential amp (Rev. A) PDF | HTML 2024/9/25
電子書 Engineer's Guide to High-Speed Amplifiers PDF | HTML 2023/10/18
應用說明 Attenuator Amplifier Design to Maximize the Input Voltage of Differential ADCs 2018/6/14
電子書 The Signal e-book: A compendium of blog posts on op amp design topics PDF | HTML 2017/3/28
應用說明 Fully-Differential Amplifiers (Rev. E) 2016/9/19
更多文件說明 Featured High Speed Differential Amplifiers 2012/10/23
類比設計期刊 Converting single-ended video to differential video in single-supply systems 2011/9/16
類比設計期刊 Using single-supply fully diff. amps with neg. input voltages to drive ADCs 2010/11/15
應用說明 DC Output Errors in a Fully-Differential Amplifier 2010/5/25
類比設計期刊 Using fully differential op amps as attenuators, Part 3 2009/10/4
類比設計期刊 Using fully differential op amps as attenuators, Part 2 2009/7/14
類比設計期刊 Using fully differential op amps as attenuators, Part 1 2009/5/1
類比設計期刊 Analysis of fully differential amplifiers 2005/3/11
類比設計期刊 Designing for low distortion with high-speed op amps 2005/3/2
應用說明 Noise Analysis for High Speed Op Amps (Rev. A) 2005/1/17

設計與開發

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開發板

REF6025EVM-PDK — REF6025 電壓參考評估模組

REF6025EVM-PDK 是評估 REF6025 電壓參考性能的平台。評估套件可展現裝置的突衝模式性能，這是裝置的主要功能。
使用指南: PDF
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開發板

THS4521EVM — THS4521 評估模組

The THS4521EVM is an evaluation module for the single, THS4521 in the D (8-lead SOIC) package.

The THS4521EVM is designed to quickly and easily demonstrate the functionality and versatility of the amplifier. The EVM is ready to connect to power, signal source, and test instruments through the use of (...)

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模擬型號

THS4521 PSpice Model (Rev. E)

SBOM343E.ZIP (36 KB) - PSpice 模型
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模擬型號

THS4521 TINA-TI Reference Design (Rev. E)

SBOM341E.TSC (1619 KB) - TINA-TI 參考設計
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模擬型號

THS4521 TINA-TI Spice Model (Rev. D)

SBOM342D.ZIP (16 KB) - TINA-TI Spice 模型
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計算工具

SBOR022 — TI FDA Calculator

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參考設計

TIDA-00499 — 使用差動放大器和 HS ADC 的暫態及數位故障記錄器 AFE 參考設計

數位故障記錄器 (DFR) 可在 60/50 Hz 下偵測 17/20 μs 的暫態，而暫態記錄器則可擷取能在毫秒內達到峰值與衰退的干擾。此參考設計展示以 1 MHz 擷取 DFR 暫態輸入，針對暫態構造器則以 25 MHz 擷取暫態輸入。正負暫態 (<=100-kV 峰值) 皆可視應用需求以不同解析度擷取 (12 位元至 14 位元解析度)，並使用驅動高速轉換器的差動放大器在 2 準確度內執行擷取。

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參考設計

TIDA-00715 — 適用於電壓輸出差動音訊 DAC 的高動態範圍耳機驅動器參考設計

本文介紹了一種用於驅動耳機的低 THD+N 放大器訊號鏈。此設計方案詳細闡述了根據客戶需求最佳化效能所需考慮的各種因素。

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參考設計

TIDM-ULTRASONIC-WATER-FLOW-MEASUREMENT — 超音波水流測量參考設計

此超音波水流測量系統非常適合在低至 1.4gpm 的廣泛流量範圍中，提供高準確度的測量。此設計以含離散式類比元件的單一 MCU 為基礎。其採用獨特的專用演算法，在各種操作條件下提高流量測量的穩健性和性能。此設計與適用無線 AMI 網路的 TI RF 外掛評估模組完全相容。

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TIPD115 — 採用最低失真、最低雜訊最佳化設定的 18 位元、1 MSPS 資料採集參考設計

This verified design is a high performance data acquisition system (DAQ) using an 18-bit SAR ADC, ADS8881 at a throughput of 1MSPS. This design has been optimized to provide the lowest noise & distortion solution for a full scale input sinewave of 10 KHz. This leads to a maximum possible value (...)

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TIPD117 — 適用於光學編碼器的 12 位元、1 MSPS 雙通道資料採集系統

This TI Precision Verified Design provides the theory, component selection, simulation, PCB design, and measurement details for a 12-bit 1-MSPS single supply dual channel simultaneous data acquisition system. This circuit achieves 73 dB SINAD for a 4.5 V differential signal at 2 KHz input (...)

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SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian
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