ADS8380
- 600-kHz Sample Rate
- ±2 LSB Typ, ±4 LSB Max INL
- 18-Bit NMC Ensured Over Temperature
- SINAD 91 dB, SFDR 119 dB at fi = 1 kHz
- High-Speed Serial Interface up to 40 MHz
- Onboard Reference Buffer
- Onboard 4.096-V Reference
- Pseudo-Differential Input, 0 V to 4.2 V
- Onboard Conversion Clock
- Selectable Output Format, 2s Complement or Straight Binary
- Zero Latency
- Wide Digital Supply
- Low Power:
- 115 mW at 600 kHz
- 15 mW During Nap Mode
- 10 µW During Power Down
- 28-Pin 6 x 6 QFN Package
- APPLICATIONS
- Medical Instruments
- Optical Networking
- Transducer Interface
- High Accuracy Data Acquisition Systems
- Magnetometers
The ADS8380 is a high performance 18-bit, 600-kHz A/D converter with single-ended (pseudo-differential) input. The device includes an 18-bit capacitor-based SAR A/D converter with inherent sample and hold. The ADS8380 offers a high-speed CMOS serial interface with clock speeds up to 40 MHz.
The ADS8380 is available in a 28 lead 6 × 6 QFN package and is characterized over the industrial 40°C to 85°C temperature range.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 18-Bit 600-kHz Pseudo-Diff Input MicroPower Sampling Analog-to-Digit Converter datasheet (Rev. A) | 2004/12/20 | |||
| 白皮書 | Voltage-reference impact on total harmonic distortion | 2016/8/1 | ||||
| 電子書 | Best of Baker's Best: Precision Data Converters -- SAR ADCs | 2015/5/21 | ||||
| 應用說明 | Determining Minimum Acquisition Times for SAR ADCs, part 2 | 2011/3/17 | ||||
| 應用說明 | Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) | 2010/11/10 | ||||
| 應用說明 | Using the ADS8380 with the TMS320C6713 DSP | 2005/3/30 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面,列出各種常見計算,從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外,此計算機還與類比工程師口袋參考中描述的概念相得益彰。
JITTER-SNR-CALC — Jitter and SNR calculator
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RHP) | 28 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。