AFE7684
- 14-Bit resolution
- Sample rate:
- DAC: 9GSPS
- ADC: 3GSPS
- RF Frequency range: up to 5.2 GHz
- Maximum RF signal bandwidth
- Quad-channel mode (4T4R): 800 MHz (single-band); 300 MHz (dual-band)
- Dual-channel mode (2T2R): 1200 MHz (TX)/1000 MHz (RX) (single-band); 800MHz(dual-band)
- On-chip dual selectable DSAs per RX channel
- Integrated TX DSA functionality
- Digital:
- Dual band digital up-converters (DUCs)
- Dual Band digital down-converters (DDCs)
- 32-Bit NCOs for DUCs/DDCs
- Interpolation ratio: 6x, 8x, 9x, 12x, 16x, 18x, 24x, 36x
- Decimation ratio: /2, /3, /4, /6, /8, /9, /12, /16, /18, /24, /32
- RX/FB Dynamic switching for TDD
- Interface:
- 8 SerDes Transceivers up to 15Gbps
- 16-Bit and 12-bit JESD204B transport layer formatting with 8b/10b encoding
- Subclass 1 multi-device synchronization
- Clock:
- Internal PLL/VCO to generate DAC and ADC clocks
- Package: 17mm x 17mm FC BGA, 0.8mm pitch
- Power supplies: 1.85 V, 1.15 V, 1.0 V, –1.8 V
The AFE76xx is a family of high performance, quad/dual channel, 14-bit, integrated RF sampling analog front ends (AFEs) with 9 GSPS DACs and 3 GSPS ADCs, capable of synthesizing and digitizing wideband signals. High dynamic range allows the AFE76xx to generate and digitize 3G/4G signals for wireless base stations. In TDD mode, the receiver channel can be configured to dynamically switching between traffic receiver (TDD RX) status and wideband feedback receiver (TDD FB) status to assist DPD (Digital Pre-Distortion) of the Power Amplifier (PA) on the transmitter path.
The AFE76xx family has integrated DSA on the receiver channels and also supports DSA equivalent functionality on the transmitter channels. Each receiver channel has one analog RF peak power detector and various digital power detectors to assist AGC control for receiver channels, and two RF overload detectors for device reliability protection. The AFE76xx family has 8 of JESD204B compatible SerDes transceivers running up to 15 Gbps. The devices have up to two DUCs per TX channel and two DDCs per RX channel, with multiple interpolation/decimation rates and digital quadrature modulators/demodulators with independent, frequency flexible NCOs. The devices support more than 1000 MHz (800 MHz as 4T4R) RF signal bandwidth in single-band mode, and up to 800 MHz (300 MHz as 4T4R) RF signal bandwidth per band in dual-band mode. A low jitter PLL/VCO simplifies the sampling clock generation by allowing use of a lower frequency reference clock.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | AFE76xx Quad/dual-channel, RF sampling analog front-end with 14-bit 9GSPS DACs and 14-bit 3GSPS ADCs datasheet (Rev. E) | PDF | HTML | 2019/3/1 | ||
| 應用說明 | Small Cell and Repeater System Using Integrated RF Sampling Device (Rev. A) | 2021/9/2 | ||||
| 應用說明 | MIMO Transceiver with AFE76xx for LTE and 5G Wireless Radio (Rev. A) | 2021/9/2 | ||||
| 應用說明 | Temp Profile to Maintain Optimum FIT Performance | 2019/7/23 | ||||
| 應用說明 | RF Sampling for Multi-band Radios | 2018/11/26 | ||||
| 應用說明 | AFE76xx as a Single-Chip Wideband Repeater Using Loopback Mode | 2018/11/1 |
設計與開發
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TI204C-IP — Request for JESD204 rapid design IP
JESD204 快速設計 IP 被設計用於幫助 FPGA 工程師快速實現可運作的 JESD204 系統,從而加速開發過程。該 IP 的架構設計使得下游數位處理和其他應用邏輯能夠隔離於 JESD204 通訊協定的大多數性能和時序關鍵約束之外。該 IP 能夠幫助設計人員減少韌體開發時間並簡化 FPGA 的整合。
JESD204 快速設計 IP 無需權利金,用於 TI 高速資料轉換器。TI 將協助使用者配置初始連結,針對特定 FPGA 平台與 TI 資料轉換器 JMODE 之間的使用進行自訂。TI 將在 IP 測試完成並準備部署後,透過安全下載連結提供 IP。
JESD204 快速設計 IP 支援下列 (...)
DATACONVERTERPRO-SW — 高速資料轉換器 Pro GUI 安裝程式,v5.31
這款高速資料轉換器專業 GUI 是一款 PC(與 Windows® XP/7/10 相容)程式,旨在協助評估大多數 TI 高速資料轉換器 [類比轉數位轉換器 (ADC) 和數位轉類比轉換器 (DAC)] 和類比前端 (AFE) 平台。DATACONVERTERPRO-SW 旨在支援整個 TSW14xxx 系列資料擷取和模式產生卡,為時域和頻域中的資料轉換器分析提供強大且快速的解決方案,並支援單音、多音和調變訊號。此 GUI 也與 TI 模式產生 GUI 相容,可快速合成單音、多音和調變訊號。
使用者可以向 DATACONVERTERPRO-SW 提供自訂模式,以載入到 TI DAC。支援從 (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCBGA (ABJ) | 400 | Ultra Librarian |