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AFE79XX-WI-DESIGN — AFE79xx Design Resources for Wireless infrastructure
AFE79xx Design Resources for Wireless infrastructure
產品規格表
AFE7989
- Quad RF sampling 12-GSPS transmit DACs
- Quad RF sampling 3-GSPS receive ADCs
- Dual RF sampling 3-GSPS feedback ADCs (AFE792x only)
- Maximum RF signal bandwidth:
- TX/FB: 1200 MHz (AFE7920/88) or 400 MHz (AFE7989) or 800MHz (AFE7921)
- RX: 600 MHz (AFE7920/88) or 400 MHz (AFE7921/AFE7989)
- Digital Step Attenuators (DSA):
- TX: 40 dB range, 1-dB analog and 0.125-dB digital steps
- RX: 25 dB range, 0.5-dB steps
- FB: 25 dB range, 0.5-dB steps
- Single or dual-band DUC/DDCs (AFE7920/88 only) for TX and RX
- Dual NCOs for fast frequency switching
- Supports TDD operation with fast switching between TX and RX
- Internal PLL/VCO to generate DAC/ADC clocks
- Optional external CLK at DAC or ADC rate
- SerDes data interface:
- JESD204B and JESD204C compliant
- 8 SerDes transceivers up to 29.5 Gbps
- 8b/10b and 64b/66b encoding
- 12-bit, 16-bit, 24-bit, and 32-bit resolution
- Subclass 1 multi-device synchronization
- Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch
The AFE79xx is a family of high performance, wide bandwidth multi-channel transceivers, integrating four RF sampling transmitter chains, four RF sampling receiver chains, and up to two RF sampling digitizing auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains allows the device to generate and receive 3G, 4G, and 5G signals from wireless base stations, while the wide bandwidth capability of the AFE79xx devices is designed for multi-band 4G and 5G base stations.
Each receiver chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a 3-GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. The single or dual digital down converters (DDC) provide up to 600 MHz of combined signal BW. In TDD mode, the receiver channel can be configured to dynamically switch between the traffic receiver (TDD RX) and wideband feedback receiver (TDD FB), with the capability of re-using the same analog input for both purposes.
Each transmitter chain includes a single or dual digital up converters (DUCs) supporting up to 1200-MHz combined signal bandwidth. The output of the DUCs drives a 12-GSPS DAC (digital to analog converter) with a mixed mode output option to enhance 2nd or 3rd Nyquist operation. The DAC output includes a variable gain amplifier (TX DSA) with 40-dB range and 1-dB analog and 0.125-dB digital steps.
The feedback path includes an 25-dB range DSA driving a 3-GSPS RF sampling ADC, followed by a DDC with up to 1200-MHz bandwidth.
技術文件
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檢視所有 7 | 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | AFE79xx Quad-Channel RF Transceiver With Feedback Path datasheet (Rev. C) | PDF | HTML | 2020年 6月 23日 |
| Application note | RF Sampling Resource Guide | PDF | HTML | 2024年 3月 5日 | |
| User guide | Interfacing AFE7769DEVM With the Hitek Agilex eSOM7 FPGA | PDF | HTML | 2023年 9月 28日 | |
| Application note | AFE79xx Layout Guide (Rev. B) | 2021年 4月 6日 | ||
| Application note | System Design Considerations when Upgrading from JESD204B to JESD204C (Rev. A) | 2021年 4月 5日 | ||
| Application note | AFE76xx, AFE77xx, and AFE79xx JESD204 Layer Testing | 2020年 4月 15日 | ||
| Application note | Temp Profile to Maintain Optimum FIT Performance | 2019年 7月 23日 |
設計與開發
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開發板
AFE7920EVM — 四發射四接收二回饋路徑射頻取樣收發器的 AFE7920 評估模組
AFE7920 評估模組 (EVM) 是射頻取樣收發器與平台，可配置為支援最多同時四個發射與兩個回饋 (4T4R + 2FB)通道。
評估 AFE7920 裝置的板為配備 14 位元 12-GSPS 數位轉類比轉換器 (DAC)、14 位元 3-GSPS 類比轉數位轉換器 (ADC)，以及適用 DAC 和 ADC 高頻率時脈產生的晶片整合式相鎖迴路 (PLL) 與電壓控制振盪器 (VCO) 之四通道射頻取樣類比前端 (AFE)。
AFE7920EVM 可選擇在每個通道中使用雙數位上變頻器和下變頻器，以同時合成及數位化具有高動態範圍的多個寬頻訊號。支援接收器通道的晶片內建整合式數位步進衰減器 (...)
開發板
HTK-3P-AGILEX-ESOM7 — HITEK Agilex eSOM7 with FMC+ connector to RF transceiver EVMs
The Hitek Systems eSOM7 interfaces with the AFE8092, AFE8030, AFE7952, and AFE7920 through an FPGA mezzanine card (FMC) connector. It provides a quick evaluation and prototyping platform for 5G wireless solutions based on Intel’s latest high-performance 10-nm Agilex F-Series FPGA.
韌體
TI204C-IP — Request for JESD204 rapid design IP
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
支援產品和硬體
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCBGA (ABJ) | 400 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點