產品詳細資料

Technology family AC Bits (#) 9 Rating Military Operating temperature range (°C) -55 to 125
Technology family AC Bits (#) 9 Rating Military Operating temperature range (°C) -55 to 125
CDIP (J) 14 130.4652 mm² 19.56 x 6.67
  • Buffered Inputs
  • Typical Propagation Delay
    - 10ns at VCC = 5V, TA = 25°C, CL = 50pF
  • Exceeds 2kV ESD Protection per MIL-STD-883, Method 3015
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
  • ±24mA Output Drive Current
    - Fanout to 15 FAST™ ICs
    - Drives 50 Transmission Lines
  • Characterized for operation from –40° to 85°C

FAST™ is a Trademark of Fairchild Semiconductor.

  • Buffered Inputs
  • Typical Propagation Delay
    - 10ns at VCC = 5V, TA = 25°C, CL = 50pF
  • Exceeds 2kV ESD Protection per MIL-STD-883, Method 3015
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
  • ±24mA Output Drive Current
    - Fanout to 15 FAST™ ICs
    - Drives 50 Transmission Lines
  • Characterized for operation from –40° to 85°C

FAST™ is a Trademark of Fairchild Semiconductor.

The ’AC280 and ’ACT280 are 9-bit odd/even parity generator/checkers that utilize Advanced CMOS Logic technology. Both even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even parity is indicated (E output to any input of an additional ’AC280, ’ACT280 parity checker.

The ’AC280 and ’ACT280 are 9-bit odd/even parity generator/checkers that utilize Advanced CMOS Logic technology. Both even and odd parity outputs are available for checking or generating parity for words up to nine bits long. Even parity is indicated (E output to any input of an additional ’AC280, ’ACT280 parity checker.

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技術文件

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類型 標題 日期
* Data sheet 9-Bit Odd/Even Parity Generator/Checker datasheet (Rev. A) 2000年 5月 17日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
More literature HiRel Unitrode Power Management Brochure 2009年 7月 7日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
CDIP (J) 14 Ultra Librarian

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