CD74HCT147

Name: CD74HCT147
Brand: TI
SKU: CD74HCT147
Price: 0.267 USD

現行

高速 CMOS 邏輯 10 至 4 線優先級編碼器

立即訂購

產品規格表

document-pdfAcrobat CD54HC147, CD74HC147, CD74HCT147 datasheet (Rev. F) (英文)

CD74HCT147

現行

產品規格表

立即訂購

產品詳細資料

Technology family

HCT

Function

Encoder

Configuration

10:4

Number of channels

1

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Technology family

HCT

Function

Encoder

Configuration

10:4

Number of channels

1

Operating temperature range (°C)

-55 to 125

Rating

Catalog

PDIP (N)

16

181.42 mm² 19.3 x 9.4

Buffered Inputs and Outputs
Typical Propagation Delay: 13ns at V_CC = 5V, C_L = 15pF, T_A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
Wide Operating Temperature Range... –55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Data sheet acquired from Harris Semiconductor

Buffered Inputs and Outputs
Typical Propagation Delay: 13ns at V_CC = 5V, C_L = 15pF, T_A = 25°C
Fanout (Over Temperature Range)
- Standard Outputs...10 LSTTL Loads
- Bus Driver Outputs...15 LSTTL Loads
Wide Operating Temperature Range... –55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Data sheet acquired from Harris Semiconductor

The ’HC147 and CD74HCT147 are high speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL).

The ’HC147 and CD74HCT147 9-input priority encoders accept data from nine active LOW inputs (l₁ to l₉) and provide binary representation on the four active LOW inputs (Y0\ to Y3\). A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line l₉ having the highest priority.

These devices provide the 10-line to 4-line priority encoding function by use of the implied decimal "zero". The "zero" is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH.

The ’HC147 and CD74HCT147 are high speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL).

The ’HC147 and CD74HCT147 9-input priority encoders accept data from nine active LOW inputs (l₁ to l₉) and provide binary representation on the four active LOW inputs (Y0\ to Y3\). A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output, with input line l₉ having the highest priority.

These devices provide the 10-line to 4-line priority encoding function by use of the implied decimal "zero". The "zero" is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH.

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