封裝資訊
| 封裝 | 針腳 TSSOP (PW) | 16 |
| 操作溫度範圍 (°C) -40 to 85 |
| 包裝數量 | 運送業者 90 | TUBE |
CDCE925 的特色
- Member of programmable clock
generator family
- CDCEx913: 1PLL, 3 Outputs
- CDCEx925: 2PLL, 5 Outputs
- CDCEx925: 3PLL, 7 Outputs
- CDCEx949: 4PLL, 9 Outputs
- In-system programmability and
EEPROM
- Serial programmable volatile register
- Nonvolatile EEPROM to store customer settings
- Flexible input clocking concept
- External crystal: 8MHz to 32MHz
- On-chip VCXO: pull range ±150ppm
- Single-ended LVCMOS up to 160MHz
- Free selectable output frequency up to 230MHz
- Low-noise PLL core
- PLL loop filter components integrated
- Low period jitter (typical 60ps)
- Separate output supply pins
- CDCE925: 3.3V and 2.5V
- CDCEL925: 1.8V
- Flexible clock driver
- Three user-definable control inputs [S0/S1/S2], for example, SSC selection, frequency switching, output enable, or power down
- Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet™, and GPS
- Generates common clock frequencies used with TI DaVinci™, OMAP™, DSPs
- Programmable SSC modulation
- Enables 0PPM clock generation
- 1.8V device power supply
- Wide temperature range: –40°C to 85°C
- Packaged in TSSOP
- Development and programming kit for easy PLL design and programming TI (Pro-Clock™)
CDCE925 的說明
The CDCE925 and CDCEL925 are modular PLL-based low-cost, high-performance, programmable clock synthesizers, multipliers, and dividers. CDCE925 and CDCEL925 generate up to five output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230MHz, using up to two independent configurable PLLs.
The CDCEx925 has a separate output supply pin, VDDOUT, which is 1.8V for CDCEL925 and 2.5V to 3.3V for CDCE925.
The input accepts an external crystal or LVCMOS clock signal. In case of a crystal input, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20pF. Additionally, an on-chip VCXO is selectable which allows synchronization of the output frequency to an external control signal, that is, PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth, Ethernet, GPS), or interface (USB, IEEE1394, memory stick) clocks from a 27MHz reference input frequency, for example.
All PLLs support SSC (spread-spectrum clocking). SSC can be center-spread or down-spread clocking, which is a common technique to reduce electromagnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.
The device supports nonvolatile EEPROM programming for easy customization of the device in the application. It is preset to a factory default configuration and can be reprogrammed to a different application configuration before it goes onto the PCB or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.
Three, free programmable control inputs, S0, S1, and S2, can be used to select different frequencies, or change the SSC setting for lowering EMI, or other control features like outputs disable to low, outputs in high-impedance state, power down, PLL bypass, and so forth.
The CDCx925 operates in a 1.8V environment and in a temperature range of –40°C to 85°C.