CSD22204W
- Low Resistance
- Small Footprint 1.5 mm × 1.5 mm
- Pb Free
- Gate ESD Protection
- RoHS Compliant
- Halogen Free
- Gate-Source Voltage Clamp
This –8 V, 8.2 mΩ, 1.5 mm × 1.5 mm device is designed to deliver the lowest on resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra low profile. Low on-resistance coupled with the small footprint and low profile make the device ideal for battery operated space constrained applications.
技術文件
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CSD22204W –8 V P-Channel NexFET Power MOSFET datasheet | PDF | HTML | 2015/3/9 | ||
| Application brief | Estimating Leakage Currents of Power MOSFETs | PDF | HTML | 2025/10/31 | |||
| 應用說明 | MOSFET Support and Training Tools (Rev. G) | PDF | HTML | 2025/10/27 | |||
| 應用說明 | Semiconductor and IC Package Thermal Metrics (Rev. D) | PDF | HTML | 2024/3/25 | |||
| 應用說明 | Using MOSFET Transient Thermal Impedance Curves In Your Design | PDF | HTML | 2023/12/18 | |||
| 應用說明 | Solving Assembly Issues with Chip Scale Power MOSFETs | PDF | HTML | 2023/12/14 | |||
| 應用說明 | Using MOSFET Safe Operating Area Curves in Your Design | PDF | HTML | 2023/3/13 | |||
| Application brief | Tips for Successfully Paralleling Power MOSFETs | PDF | HTML | 2022/5/31 | |||
| 應用說明 | AN-1112 DSBGA Wafer Level Chip Scale Package (Rev. AI) | 2019/6/14 |
設計與開發
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支援軟體
LOAD-SWITCH-FET-LOSS-CALC — Power Loss Calculation Tool for Load Switch
快速取捨尺寸、成本和性能，以根據應用條件選擇最佳 MOSFET。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| DSBGA (YZF) | 9 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。