DAC5687
- 500 MSPS
- Selectable 2×-8× Interpolation
- On-Chip PLL/VCO Clock Multiplier
- Full IQ Compensation Including Offset, Gain, and Phase
- Flexible Input Options:
- FIFO With Latch on External or Internal Clock
- Even/Odd Multiplexed Input
- Single Port Demultiplexed Input
- Complex Mixer With 32-Bit NCO
- Fixed Frequency Mixer With fS/4 and fS/2
- 1.8-V or 3.3-V I/O Voltage
- On-Chip 1.2-V Reference
- Differential Scalable Output: 2 mA to 20 mA
- Pin Compatible to DAC5686
- High Performance
- 81-dBc ACLR WCDMA TM1 at 30.72 MHz
- 72-dBc ACLR WCDMA TM1 at 153.6 MHz
- Package: 100-Pin HTQFP
- APPLICATIONS
- Cellular Base Transceiver Station Transmit Channel
- CDMA: W-CDMA, CDMA2000, TD-SCDMA
- TDMA: GSM, IS-136, EDGE/UWC-136
- OFDM: 802.16
- Cable Modem Termination System
- Cellular Base Transceiver Station Transmit Channel
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The DAC5687 is a dual-channel 16-bit high-speed digital-to-analog converter (DAC) with integrated 2×, 4×, and 8× interpolation filters, a complex numerically controlled oscillator (NCO), onboard clock multiplier, IQ compensation, and on-chip voltage reference. The DAC5687 is pin-compatible to the DAC5686, requiring only changes in register settings for most applications, and offers additional features and superior linearity, noise, crosstalk, and PLL phase noise performance.
The DAC5687 has six signal processing blocks: two interpolate-by-two digital filters, a fine frequency mixer with 32-bit NCO, a quadrature modulation compensation block, another interpolate-by-two digital filter, and a coarse frequency mixer with fS/2 or fS/4. The different modes of operation enable or bypass the signal processing blocks.
The coarse and fine mixers can be combined to span a wider range of frequencies with fine resolution. The DAC5687 allows both complex or real output. Combining the frequency upconversion and complex output produces a Hilbert transform pair that is output from the two DACs. An external RF quadrature modulator then performs the final single-sideband upconversion.
The IQ compensation feature allows optimization of phase, gain, and offset to maximize sideband rejection and minimize LO feedthrough for an analog quadrature modulator.
The DAC5687 includes several input options: single-port interleaved data, even and odd multiplexing at half-rate, and an input FIFO with either external or internal clock to ease the input timing ambiguity when the DAC5687 is clocked at the DAC output sample rate.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 16-Bit 500 MSPS 2x-8x Interpolating Dual-Channel DAC datasheet (Rev. E) | 2006/9/20 | |||
| 類比設計期刊 | Q3 2009 Issue Analog Applications Journal | 2018/9/24 | ||||
| 應用說明 | High Speed, Digital-to-Analog Converters Basics (Rev. A) | 2012/10/23 | ||||
| 類比設計期刊 | Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs | 2009/7/14 | ||||
| 應用說明 | Passive Terminations for Current Output DACs | 2008/11/10 | ||||
| 應用說明 | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008/6/8 | ||||
| 應用說明 | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008/6/2 | ||||
| 使用指南 | TSW3003 Demonstration Kit (Rev. D) | 2007/8/28 | ||||
| Product overview | TSW3003: RF Transmit Signal Chain Demonstration Kit Bulletin | 2006/9/28 | ||||
| Product overview | TSW3000: DAC5687 and TRF3701/02 16-Bit, 500 MSPS DAC Coupled with Direct IQ Modu | 2005/9/14 | ||||
| 應用說明 | DAC5686/DAC5687 Clock Generation Using PLL & External Clock Modes (Rev. A) | 2005/7/21 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| HTQFP (PZP) | 100 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。