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運算放大器 (op amps)
高速運算放大器 (GBW ≥ 50 MHz)

OPA2626

現行

高頻寬、高精度、低 THD+N、16 位元和 18 位元 ADC 驅動器

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產品規格表

OPA2626

現行
產品規格表 立即訂購

產品詳細資料

Architecture Voltage FB Number of channels 2 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.7 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.5 GBW (typ) (MHz) 120 BW at Acl (MHz) 120 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 115 Vn at flatband (typ) (nV√Hz) 2.5 Vn at 1 kHz (typ) (nV√Hz) 3.2 Iq per channel (typ) (mA) 2 Vos (offset voltage at 25°C) (max) (mV) 0.1 Rail-to-rail In to V-, Out Rating Catalog Operating temperature range (°C) -40 to 125 CMRR (typ) (dB) 117 Input bias current (max) (pA) 4000000 Offset drift (typ) (µV/°C) 0.5 Iout (typ) (mA) 100 2nd harmonic (dBc) 155 3rd harmonic (dBc) 144 Frequency of harmonic distortion measurement (MHz) 0.01
Architecture Voltage FB Number of channels 2 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.7 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.5 GBW (typ) (MHz) 120 BW at Acl (MHz) 120 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 115 Vn at flatband (typ) (nV√Hz) 2.5 Vn at 1 kHz (typ) (nV√Hz) 3.2 Iq per channel (typ) (mA) 2 Vos (offset voltage at 25°C) (max) (mV) 0.1 Rail-to-rail In to V-, Out Rating Catalog Operating temperature range (°C) -40 to 125 CMRR (typ) (dB) 117 Input bias current (max) (pA) 4000000 Offset drift (typ) (µV/°C) 0.5 Iout (typ) (mA) 100 2nd harmonic (dBc) 155 3rd harmonic (dBc) 144 Frequency of harmonic distortion measurement (MHz) 0.01
VSSOP (DGK) 8 14.7 mm² (3 mm × 4.9 mm)
  • Excellent dynamic performance:
    • Low distortion: –122 dBc for HD2 and
      –140 dBc for HD3 at 100 kHz
    • Gain bandwidth (G = 100): 120 MHz
    • Slew rate: 115 V/µs
    • 16-bit settling at 4-V step: 280 ns
    • Low voltage noise: 2.5 nV/√Hz at 10 kHz
    • Low output impedance: 1 Ω at 1 MHz
  • Excellent DC precision:
    • Offset voltage: ±100 µV (maximum)
    • Offset voltage drift: ±3 µV/ºC (maximum)
    • Low quiescent current: 2 mA (typical)
  • Input common-mode range includes negative rail
  • Rail-to-rail output
  • Wide temperature range: fully specified from –40°C to +125°C
  • Excellent dynamic performance:
    • Low distortion: –122 dBc for HD2 and
      –140 dBc for HD3 at 100 kHz
    • Gain bandwidth (G = 100): 120 MHz
    • Slew rate: 115 V/µs
    • 16-bit settling at 4-V step: 280 ns
    • Low voltage noise: 2.5 nV/√Hz at 10 kHz
    • Low output impedance: 1 Ω at 1 MHz
  • Excellent DC precision:
    • Offset voltage: ±100 µV (maximum)
    • Offset voltage drift: ±3 µV/ºC (maximum)
    • Low quiescent current: 2 mA (typical)
  • Input common-mode range includes negative rail
  • Rail-to-rail output
  • Wide temperature range: fully specified from –40°C to +125°C

The OPA2626 operational amplifier is a 16-bit and 18-bit, high-precision, successive-approximation register (SAR) analog-to-digital converter (ADC) driver with low total harmonic distortion (THD) and noise. This op amp is fully characterized and specified with a 16-bit settling time of 280 ns that enables a true 16-bit effective number of bits (ENOB). With a high DC precision of only 100-µV offset voltage, a wide gain-bandwidth product of 120 MHz, and a low wideband noise of 2.5 nV/√Hz, this device is optimized for driving high-throughput, high-resolution SAR ADCs in applications such as the ADS88xx family of SAR ADCs.

The OPA2626 is available in an 8-pin VSSOP package and is specified for operation from –40°C to +125°C.

The OPA2626 operational amplifier is a 16-bit and 18-bit, high-precision, successive-approximation register (SAR) analog-to-digital converter (ADC) driver with low total harmonic distortion (THD) and noise. This op amp is fully characterized and specified with a 16-bit settling time of 280 ns that enables a true 16-bit effective number of bits (ENOB). With a high DC precision of only 100-µV offset voltage, a wide gain-bandwidth product of 120 MHz, and a low wideband noise of 2.5 nV/√Hz, this device is optimized for driving high-throughput, high-resolution SAR ADCs in applications such as the ADS88xx family of SAR ADCs.

The OPA2626 is available in an 8-pin VSSOP package and is specified for operation from –40°C to +125°C.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 OPA2626 High-Speed, High-Precision, Low-Distortion, 16-Bit and 18-Bit Analog-to-Digital Converter (ADC) Driver datasheet (Rev. A) PDF | HTML 2019/12/19
電子書 The Signal e-book: A compendium of blog posts on op amp design topics PDF | HTML 2017/3/28

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

OPA626 PSpice Model

SBOMA33.ZIP (53 KB) - PSpice 模型
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模擬型號

OPA626 TINA-TI Reference Design

SBOMA31.TSC (341 KB) - TINA-TI 參考設計
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模擬型號

OPA626 TINA-TI Spice Model

SBOMA32.ZIP (9 KB) - TINA-TI Spice 模型
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計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。

除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。

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參考設計

TIDA-01403 — 適用於熱成像攝影機的 74-dB SNR、10-MSPS、14 位元類比前端參考設計

此參考設計在打造時將電子影像系統納入考量。現今的影像感測器對 ADC 有高要求，包括：優異的線性度（DNL < 0.5 LSB 與 INL < 4 LSB）、高解析度（12 至 18 位元）、高速（高達 20MSPS）和高信噪比（SNR > 74dB），可確保優異的影像品質，並避免隨時間產生的失真問題。此參考設計有 TI 的低雜訊、高速放大器、全差動放大器 (FDA)、高速 ADC 和低雜訊 LDO，展示如何設計高性能類比訊號鏈，將熱成像攝影機中的像素輸出訊號數位化。
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
VSSOP (DGK) 8 Ultra Librarian
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