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可編程與可變增益放大器 (PGA 與 VGA)

PGA112

現行

具 2 通道多工器的零漂移、100-µV 偏移、12-nV/√Hz 雜訊、RRO (二進位增益) 可編程增益放大器

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產品規格表

PGA112

現行
產品規格表 立即訂購

產品詳細資料

PGA/VGA PGA Number of channels 2 Vs (min) (V) 2.2 Vs (max) (V) 5.5 Input type Single-ended Output type Single-ended Input offset drift (±) (typ) (µV/°C) 0.6 Interface type SPI Noise at 1 kHz (typ) (V√Hz) 0.000000013 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Gain (max) (dB) 42 Architecture CMOS Features Daisy chain, Scope gains, Shutdown Vos (offset voltage at 25°C) (typ) (mV) 0.025 Input voltage noise (typ) (µV√Hz) 0.012 Slew rate (typ) (V/µs) 3 Iq per channel (typ) (mA) 1.08 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Operating temperature range (°C) -40 to 125
PGA/VGA PGA Number of channels 2 Vs (min) (V) 2.2 Vs (max) (V) 5.5 Input type Single-ended Output type Single-ended Input offset drift (±) (typ) (µV/°C) 0.6 Interface type SPI Noise at 1 kHz (typ) (V√Hz) 0.000000013 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Gain (max) (dB) 42 Architecture CMOS Features Daisy chain, Scope gains, Shutdown Vos (offset voltage at 25°C) (typ) (mV) 0.025 Input voltage noise (typ) (µV√Hz) 0.012 Slew rate (typ) (V/µs) 3 Iq per channel (typ) (mA) 1.08 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Operating temperature range (°C) -40 to 125
VSSOP (DGS) 10 14.7 mm² (3 mm × 4.9 mm)
  • Rail-to-Rail Input and Output
  • Offset: 25 µV (Typical), 100 µV
    (Maximum)
  • Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 µA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI™ Interface (10 MHz) With Daisy-Chain
    Capability
  • Rail-to-Rail Input and Output
  • Offset: 25 µV (Typical), 100 µV
    (Maximum)
  • Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 µA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI™ Interface (10 MHz) With Daisy-Chain
    Capability

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.
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針腳對針腳的功能與所比較的裝置相同。
PGA113 現行 具 2 通道多工器的零漂移、100-µV 偏移、12-nV/√Hz 雜訊、RRO (範圍增益) 可編程增益放大器 This device offers scope gains 1, 2, 5, 10, 20, 50, 100, 200 instead of binary gains
功能相同，但針腳輸出與所比較的裝置不同。
PGA116 現行 具 10 通道多工器的零漂移、100-µV 偏移、12-nV/√Hz 雜訊、RRO (二進位增益) 可編程增益放大器 This device offers 10 channel mux instead of 2 channel mux.
PGA117 現行 具 10 通道多工器的零漂移、100-µV 偏移、12-nV/√Hz 雜訊、RRO (範圍增益) 可編程增益放大器 This device offers 10 channel mux instead of 2 channel mux, and scope gains instead of binary gains

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* 資料表 PGA11x Zerø-Drift Programmable Gain Amplifier With Mux datasheet (Rev. C) PDF | HTML 2015/11/30

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PGA112EVM-B — PGA112 評估模組 B 版

The PGA112EVM is an evaluation module that is used to fully evaluate the PGA112 programmable gain amplifier. The PGA112EVM consists of two printed circuit boards (PCBs). One board (the SM-USB-DIG Platform) generates the digital signals required to communicate with the PGA112. The second board is (...)

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SBOC272 — PGA112/113EVM Software

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SBOC426 — PGA112/113EVM Source Code

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