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非反相緩衝器和驅動器

SN74AUP1G125

現行

具有 3 態輸出的單路 0.8-V 至 3.6-V 低功耗緩衝器

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產品規格表

SN74AUP1G125

現行
產品規格表 立即訂購

產品詳細資料

Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 1 IOL (max) (mA) 4 Supply current (max) (µA) 0.9 IOH (max) (mA) -4 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 1 IOL (max) (mA) 4 Supply current (max) (µA) 0.9 IOH (max) (mA) -4 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YFP) 6 1.4000000000000001 mm² 1 x 1.4000000000000001 DSBGA (YZP) 5 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 5 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DPW) 5 0.64 mm² 0.8 x 0.8 X2SON (DSF) 6 1 mm² 1 x 1
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4 pF Typical at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    < 10% of VCC
  • Input-Disable Feature Allows Floating Input Conditions
  • Ioff Supports Partial-Power-Down Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.6 ns Maximum at 3.3 V
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4 pF Typical at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot
    < 10% of VCC
  • Input-Disable Feature Allows Floating Input Conditions
  • Ioff Supports Partial-Power-Down Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.6 ns Maximum at 3.3 V

The SN74AUP1G125 bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.

To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74AUP1G125 bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals.

To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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類型 標題 日期
* Data sheet SN74AUP1G125 Low-Power Single Bus Buffer Gate With 3-State Output datasheet (Rev. N) PDF | HTML 2017年 7月 10日
Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 2019年 5月 22日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Application note Designing and Manufacturing with TI's X2SON Packages 2017年 8月 23日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
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模擬型號

HSPICE Model for SN74AUP1G125

SCEJ267.ZIP (99 KB) - HSpice Model
下載
模擬型號

SN74AUP1G125 Behavioral SPICE Model

SCEM689.ZIP (7 KB) - PSpice Model
下載
模擬型號

SN74AUP1G125 IBIS Model (Rev. B)

SCEM460B.ZIP (79 KB) - IBIS Model
下載
參考設計

TIDA-00403 — 使用 TLV320AIC3268 miniDSP 轉碼器的超音波距離量測參考設計

The TIDA-00403 reference design uses off-the-shelf EVMs for ultrasonic distance measurement solutions using algorithms within the TLV320AIC3268 miniDSP. In conjunction with TI’s PurePath Studio design suite, a robust and user configurable ultrasonic distance measurement system can be designed (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00385 — 適用於可攜式和智慧型手機應用的高保真音訊耳機播放參考設計

Since the use of high fidelity headphones is a growing trend for portable audio playback, higher performance DAC and Headphone Amplifiers are demanded. This system converts digital audio from USB, SPDIF, or optical sources into analog using PCM5242 audio DAC. A high performance TPA6120A2 headphone (...)
Test report: PDF
電路圖: PDF
封裝 引腳 下載
DSBGA (YFP) 6 檢視選項
DSBGA (YZP) 5 檢視選項
SOT-23 (DBV) 5 檢視選項
SOT-5X3 (DRL) 5 檢視選項
SOT-SC70 (DCK) 5 檢視選項
USON (DRY) 6 檢視選項
X2SON (DPW) 5 檢視選項
X2SON (DSF) 6 檢視選項
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