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SN74AXCH1T45 現行 單位元雙電源匯流排收發器 Pin-to-pin upgrade with a wider voltage range and improved performance

產品詳細資料

Bits (#) 1 Data rate (max) (Mbps) 500 Topology Push-Pull Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications GPIO Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 4.7 Technology family AVC Supply current (max) (mA) 0.02 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 1 Data rate (max) (Mbps) 500 Topology Push-Pull Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications GPIO Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 4.7 Technology family AVC Supply current (max) (mA) 0.02 Rating Catalog Operating temperature range (°C) -40 to 85
SOT-23 (DBV) 6 8.12 mm² (2.9 mm × 2.8 mm) SOT-SC70 (DCK) 6 4.2 mm² (2 mm × 2.1 mm) DSBGA (YZP) 6 2.1875 mm² (— mm × — mm)
  • Available in Texas Instruments’ NanoStar™ integrated circuit package
  • Available in Texas Instruments’ NanoFree™ package
  • Control inputs (DIR) VIH and VIL levels are referenced to VCCA voltage
  • Bus hold on data inputs eliminates the need for external pullup and pulldown resistors
  • VCC isolation
  • Fully configurable dual-rail design
  • I/Os are 4.6V tolerant
  • Ioff supports partial-power-down mode operation
  • Typical max data rates
    • 500Mbps (1.8V to 3.3V translation)
    • 320Mbps (<1.8V to 3.3V translation)
    • 320Mbps (translate to 2.5V or 1.8V)
    • 280Mbps (translate to 1.5V)
    • 240Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • Human-Body Model (A114-A): 2000V
    • Machine Model (A115-A): 200V
    • Charged-Device Model (C101): 1000V
  • Available in Texas Instruments’ NanoStar™ integrated circuit package
  • Available in Texas Instruments’ NanoFree™ package
  • Control inputs (DIR) VIH and VIL levels are referenced to VCCA voltage
  • Bus hold on data inputs eliminates the need for external pullup and pulldown resistors
  • VCC isolation
  • Fully configurable dual-rail design
  • I/Os are 4.6V tolerant
  • Ioff supports partial-power-down mode operation
  • Typical max data rates
    • 500Mbps (1.8V to 3.3V translation)
    • 320Mbps (<1.8V to 3.3V translation)
    • 320Mbps (translate to 2.5V or 1.8V)
    • 280Mbps (translate to 1.5V)
    • 240Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • Human-Body Model (A114-A): 2000V
    • Machine Model (A115-A): 200V
    • Charged-Device Model (C101): 1000V

The SN74AVCH1T45 is a single-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB, which accepts any supply voltage from 1.2V to 3.6V. This feature allows for universal low-voltage, bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVCH1T45 is designed for asynchronous communication between two data buses. The device transmits data from either the A bus to the B bus, or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input.

The SN74AVCH1T45 is designed so that the DIR input is referenced to VCCA.

The SN74AVCH1T45 is a single-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The A port is designed to track VCCA, which accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB, which accepts any supply voltage from 1.2V to 3.6V. This feature allows for universal low-voltage, bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVCH1T45 is designed for asynchronous communication between two data buses. The device transmits data from either the A bus to the B bus, or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input.

The SN74AVCH1T45 is designed so that the DIR input is referenced to VCCA.

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設計與開發

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開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
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開發板

AVCLVCDIRCNTRL-EVM — 適用於方向控制雙向轉換裝置、支援 AVC 和 LVC 的通用 EVM

通用 EVM 的設計可支援一、二、四、八通道 LVC 及 AVC 方向控制的轉換裝置。此外也支援相同通道數量的匯流排保留與汽車 -Q1 裝置。AVC 是低電壓轉換裝置,具較低驅動強度 12mA。LVC 是較高的電壓轉換裝置,範圍從 1.65 到 5.5V 且具較高驅動強度 32mA。

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模擬型號

SN74AVCH1T45 IBIS Model (Rev. A)

SCEM438 (628 KB) - IBIS 模型
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參考設計

TIDA-00309 — DisplayPort 視訊 4:1 聚合參考設計

此經驗證的參考設計是完整的四通道 DisplayPort 聚合與去聚合解決方案。使用一個 TLK10022 將四個同步 DisplayPort (DP) 源聚合到一條 10.8Gbps 串列鏈路中。序列資料透過銅纜或光纖傳輸,其中第二個 TLK10022 用於去聚合並無縫地重新顯示原始視訊內容。

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參考設計

TIDA-00352 — SDI 視訊聚合參考設計

此經驗證的參考設計是完整的四通道 SDI 聚合與去聚合解決方案。一個 TLK10022 用於將四個同步 HD-SDI 源聚合到一個 5.94Gbps 串列鏈路中。序列資料透過銅纜或光纖傳輸,其中第二個 TLK10022 用於去聚合並無縫地重新顯示原始視訊內容。

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOT-23 (DBV) 6 Ultra Librarian
SOT-SC70 (DCK) 6 Ultra Librarian
DSBGA (YZP) 6 Ultra Librarian

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