Product details

Operating temperature range (C) -40 to 85
Operating temperature range (C) -40 to 85
FCBGA (CTR) 144 169 mm² 13 x 13
  • Automatic Digital Multiplexing/De-Multiplexing of 4,
    3, or 2 Independent Lower-Speed Gigabit Serial Lines
    into a Single Higher-Speed Gigabit Serial Line
  • 4 × (0.25 to 2.5 Gbps) to 1 × (1 to 10 Gbps) Multiplexing
  • 3 × (0.5 to 3.33 Gbps) to 1× (1.5 to 10 Gbps)
  • 2 × (0.5 to 5 Gbps) to 1 × (1 to 10 Gbps)
  • 1 × (0.5 to 2.5 Gbps) to 1 × (0.5 to 2.5 Gbps)
  • Programmable Per Channel Lane Switching
  • Wide Data Rate Range for Multiple Application Support
  • Transmit De-Emphasis and Adaptive Receiver Equalization
    on Both Low Speed and High Speed Sides
  • 8B/10B ENDEC Coding Support
  • Raw (unencoded) Data Support
  • Core Supply 1V; I/O: 1.5V/1.8V
  • Programmable High Speed Scrambling/Descrambling Functions
    Improve Serial Link Transition Density and Reduce Spectral Peaks
  • Superior Signal Integrity Performance
  • Low Power Operation: < 800mW per Channel (typ)
  • Flexible Clocking
  • Multi Drive Capability (SFP+, backplane, cable)
  • Support for Programmable Lane Marker Character
  • Support for Programmable HS/LS 10-Bit Alignment Character
  • Wide Range of Built-in Test Patterns
  • 144-pin, 13mmx13mm FCBGA Package
  • Automatic Digital Multiplexing/De-Multiplexing of 4,
    3, or 2 Independent Lower-Speed Gigabit Serial Lines
    into a Single Higher-Speed Gigabit Serial Line
  • 4 × (0.25 to 2.5 Gbps) to 1 × (1 to 10 Gbps) Multiplexing
  • 3 × (0.5 to 3.33 Gbps) to 1× (1.5 to 10 Gbps)
  • 2 × (0.5 to 5 Gbps) to 1 × (1 to 10 Gbps)
  • 1 × (0.5 to 2.5 Gbps) to 1 × (0.5 to 2.5 Gbps)
  • Programmable Per Channel Lane Switching
  • Wide Data Rate Range for Multiple Application Support
  • Transmit De-Emphasis and Adaptive Receiver Equalization
    on Both Low Speed and High Speed Sides
  • 8B/10B ENDEC Coding Support
  • Raw (unencoded) Data Support
  • Core Supply 1V; I/O: 1.5V/1.8V
  • Programmable High Speed Scrambling/Descrambling Functions
    Improve Serial Link Transition Density and Reduce Spectral Peaks
  • Superior Signal Integrity Performance
  • Low Power Operation: < 800mW per Channel (typ)
  • Flexible Clocking
  • Multi Drive Capability (SFP+, backplane, cable)
  • Support for Programmable Lane Marker Character
  • Support for Programmable HS/LS 10-Bit Alignment Character
  • Wide Range of Built-in Test Patterns
  • 144-pin, 13mmx13mm FCBGA Package

The TLK10022 is a dual-channel multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems. The device allows for a reduction in the number of physical links required for a certain data throughput by multiplexing multiple lower-rate serial links into higher-rate serial links.

Each channel of the TLK10022 has a low-speed interface which can accommodate one, two, three, or four bidirectional serial links running at rates from 250 Mbps to 5 Gbps (maximum of 10 Gbps total throughput). The device’s high speed interfaces (one per channel, bidirectional) can operate at rates from 1 Gbps to 10 Gbps. When a channel is configured for a certain multiplexing ratio (1-to-1, 2-to-1, 3-to-1, or 4-to-1), the high speed side will operate at a fixed multiple of the low speed rate (e.g., four times faster for 4-to-1 mode) regardless of the number of lanes connected. Filler data will be placed on any unused lanes in order to keep the interleaved lane ordering constant. This allows for low speed lanes to be hot swapped during normal operation without requiring a change in configuration.

The device has multiple interleaving/de-interleaving schemes that may be used depending on the data type. These schemes allow for the low speed lane ordering to be recovered after the lanes are transmitted over a single high-speed link. There is also a programmable scrambling/de-scrambling function available to help ensure that the high-speed data has suitable properties for transmission (i.e., sufficient transition density for clock recovery and DC balance over time) even for non-ideal input data.

A 1:1 mode is also supported for data rates ranging from 0.5 Gbps to 2.5 Gbps, whereby both low speed and high speed are rate matched. The TX and RX datapaths are also independent, so the TX and RX can operates in different modes (this excludes 3:1 mode which requires both the TX and RX path to run in the same mode). This independence is restricted to using the same low speed line rate. For example, the TX can operate at 4 × 2.5 Gbps while RX operates at 1 x 2.5 Gbps.

The individual Low Speed lanes may also operate at independent rates in byte interleave mode, provided they are operating at integer multiples. The High Speed line rate must be configured based on the fastest Low Speed line rate.

The TLK10022 has the ability to perform lane alignment on 2, 3, or 4 lanes with up to four bytes of lane de-skew.

Both the low speed and high speed side interfaces (transmitters and receivers) use CML signaling with integrated termination resistors and feature programmable transmitter de-emphasis levels and adaptive receive equalization to help compensate for media impairments at higher frequencies. The device’s serial transceivers used are capable of interfacing to optical modules as well as higher-loss connections such as PCB backplanes and controlled-impedance copper cabling.

To aid in system synchronization, the TLK10022 is capable of extracting clocking information from the serial input data streams and outputting a recovered clock signal. This recovered clock can be input to a jitter cleaner in order to provide a synchronized system clock. The device also has two reference clock input ports and a flexible internal PLL, allowing for various serial rates to be supported with a single reference clock input frequency.

The device has various built-in self-test features to aid with system validation and debugging. Among these are pattern generation and verification on all serial lanes as well as internal data loopback paths.

The TLK10022 is a dual-channel multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems. The device allows for a reduction in the number of physical links required for a certain data throughput by multiplexing multiple lower-rate serial links into higher-rate serial links.

Each channel of the TLK10022 has a low-speed interface which can accommodate one, two, three, or four bidirectional serial links running at rates from 250 Mbps to 5 Gbps (maximum of 10 Gbps total throughput). The device’s high speed interfaces (one per channel, bidirectional) can operate at rates from 1 Gbps to 10 Gbps. When a channel is configured for a certain multiplexing ratio (1-to-1, 2-to-1, 3-to-1, or 4-to-1), the high speed side will operate at a fixed multiple of the low speed rate (e.g., four times faster for 4-to-1 mode) regardless of the number of lanes connected. Filler data will be placed on any unused lanes in order to keep the interleaved lane ordering constant. This allows for low speed lanes to be hot swapped during normal operation without requiring a change in configuration.

The device has multiple interleaving/de-interleaving schemes that may be used depending on the data type. These schemes allow for the low speed lane ordering to be recovered after the lanes are transmitted over a single high-speed link. There is also a programmable scrambling/de-scrambling function available to help ensure that the high-speed data has suitable properties for transmission (i.e., sufficient transition density for clock recovery and DC balance over time) even for non-ideal input data.

A 1:1 mode is also supported for data rates ranging from 0.5 Gbps to 2.5 Gbps, whereby both low speed and high speed are rate matched. The TX and RX datapaths are also independent, so the TX and RX can operates in different modes (this excludes 3:1 mode which requires both the TX and RX path to run in the same mode). This independence is restricted to using the same low speed line rate. For example, the TX can operate at 4 × 2.5 Gbps while RX operates at 1 x 2.5 Gbps.

The individual Low Speed lanes may also operate at independent rates in byte interleave mode, provided they are operating at integer multiples. The High Speed line rate must be configured based on the fastest Low Speed line rate.

The TLK10022 has the ability to perform lane alignment on 2, 3, or 4 lanes with up to four bytes of lane de-skew.

Both the low speed and high speed side interfaces (transmitters and receivers) use CML signaling with integrated termination resistors and feature programmable transmitter de-emphasis levels and adaptive receive equalization to help compensate for media impairments at higher frequencies. The device’s serial transceivers used are capable of interfacing to optical modules as well as higher-loss connections such as PCB backplanes and controlled-impedance copper cabling.

To aid in system synchronization, the TLK10022 is capable of extracting clocking information from the serial input data streams and outputting a recovered clock signal. This recovered clock can be input to a jitter cleaner in order to provide a synchronized system clock. The device also has two reference clock input ports and a flexible internal PLL, allowing for various serial rates to be supported with a single reference clock input frequency.

The device has various built-in self-test features to aid with system validation and debugging. Among these are pattern generation and verification on all serial lanes as well as internal data loopback paths.

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Technical documentation

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Type Title Date
* Data sheet TLK10022 10Gbps Dual-Channel Multi-Rate Serial Link Aggregator datasheet 07 Nov 2013
Technical article Get Connected: Data aggregation using a general purpose SerDes 17 Dec 2014
Application note Video Aggregation HD-SDI Interface Application Sheet 01 Oct 2014
Application note Video Aggregation – Display Port Interface Application Sheet 16 Dec 2013
EVM User's guide TLK10022 and TLK10081 EVM User's Guide 08 Nov 2013
User guide TLK10022 and TLK10081 Multi-Rate Lane Aggregator EVM GUI User's Guide 08 Nov 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TLK10022EVM — TLK10022EVM - Motherboard Evaluation Module for 10Gbps Multi-Rate Universal Link Aggregator

This motherboard evaluation board for TLK10022 comes with custom-developed GUI and a detailed EVM user guide. The EVM along with the GUI, enable customers to configure the registers of all the channels independently and to debug the device. The user’s guide provides guidance on proper use of (...)

User guide: PDF
GUI for evaluation module (EVM)

TLK10022/81 EVM GUI Software

SLLC440.ZIP (37141 KB)
Simulation model

TLK10022 IBIS Model

SLLM231.ZIP (60 KB) - IBIS Model
Simulation model

TLK10022 Hspice Model

SLLM232.ZIP (9164 KB) - HSpice Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Reference designs

TIDA-00352 — SDI Video Aggregation Reference Design

This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is (...)
Schematic: PDF
Reference designs

TIDA-00309 — DisplayPort Video 4:1 Aggregation Reference Design

This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a (...)
Schematic: PDF
Package Pins Download
FCBGA (CTR) 144 View options

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