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電壓轉換器及電平移位器
電壓轉換器

SN74AXC1T45

現行

單位元雙電源匯流排收發器

立即訂購
產品規格表

SN74AXC1T45

現行
產品規格表 立即訂購

產品詳細資料

Technology family AXC Bits (#) 1 Data rate (max) (bps) 380000000 High input voltage (min) (V) 0.455 High input voltage (max) (V) 3.6 Vout (min) (V) 0.65 IOH (max) (A) -0.012 IOL (max) (A) 0.012 Supply current (max) (A) 0.000012 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 125 Applications GPIO Rating Catalog
Technology family AXC Bits (#) 1 Data rate (max) (bps) 380000000 High input voltage (min) (V) 0.455 High input voltage (max) (V) 3.6 Vout (min) (V) 0.65 IOH (max) (A) -0.012 IOL (max) (A) 0.012 Supply current (max) (A) 0.000012 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 125 Applications GPIO Rating Catalog
SOT-23 (DBV) 6 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 6 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1 X2SON (DEA) 6 1 mm² 1 x 1 X2SON (DTQ) 6 0.8 mm² 1 x 0.8
  • Up and down translation across 0.65 V to 3.6 V
  • Operating temperature: –40°C to +125°C
  • Designed with glitch suppression circuitry to improve power sequencing performance
  • Maximum quiescent current (ICCA + ICCB) of 10µA (85°C maximum) and 16µA (125°C maximum)
  • Up to 500Mbps support when translating from 1.8 to 3.3V
  • VCC isolation feature:
    • If either VCC input is below 100mV, all I/Os outputs are disabled and become high-impedance
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000-V human body model
    • 1000-V charged-device model
  • Up and down translation across 0.65 V to 3.6 V
  • Operating temperature: –40°C to +125°C
  • Designed with glitch suppression circuitry to improve power sequencing performance
  • Maximum quiescent current (ICCA + ICCB) of 10µA (85°C maximum) and 16µA (125°C maximum)
  • Up to 500Mbps support when translating from 1.8 to 3.3V
  • VCC isolation feature:
    • If either VCC input is below 100mV, all I/Os outputs are disabled and become high-impedance
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000-V human body model
    • 1000-V charged-device model

The SN74AXC1T45 is a single-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The device is operational with both VCCA and VCCB supplies as low as 0.65 V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6V. The B port is designed to track VCCB, which also accepts any supply voltage from 0.65 V to 3.6V.

The DIR pin determines the direction of signal propagation. With the DIR pin configured HIGH, translation is from Port A to Port B. With DIR configured LOW, translation is from Port B to Port A. The DIR pin is referenced to VCCA, meaning that its logic-high and logic-low thresholds track with VCCA.

This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down.

The VCC isolation feature ensures that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling their outputs.

The glitch suppression circuitry enables either supply rail to be powered on or off in any order, providing robust power sequencing performance.

The SN74AXC1T45 is a single-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The device is operational with both VCCA and VCCB supplies as low as 0.65 V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6V. The B port is designed to track VCCB, which also accepts any supply voltage from 0.65 V to 3.6V.

The DIR pin determines the direction of signal propagation. With the DIR pin configured HIGH, translation is from Port A to Port B. With DIR configured LOW, translation is from Port B to Port A. The DIR pin is referenced to VCCA, meaning that its logic-high and logic-low thresholds track with VCCA.

This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down.

The VCC isolation feature ensures that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling their outputs.

The glitch suppression circuitry enables either supply rail to be powered on or off in any order, providing robust power sequencing performance.
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類型 標題 日期
* Data sheet SN74AXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation datasheet (Rev. E) PDF | HTML 2024年 1月 12日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Application brief Future-Proofing Your Level Shifter Design with TI's Dual Footprint Packages PDF | HTML 2023年 9月 5日
Application brief Translate Voltages for MDIO PDF | HTML 2021年 7月 16日
EVM User's guide AXC Small-Package Evaluation Module User's Guide (Rev. A) PDF | HTML 2021年 7月 12日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Application note Low Voltage Translation for SPI, UART, RGMII, JTAG Interfaces (Rev. B) PDF | HTML 2021年 3月 29日
Application note Translate Voltages for GPIO PDF | HTML 2020年 8月 4日
Technical article Enabling IIoT to reach beyond the factory floor PDF | HTML 2020年 7月 29日
Technical article A glitch in your system’s matrix? PDF | HTML 2019年 4月 11日
Application brief How to Support 1.8-V Signals Using a 3.3-V LVDS Driver/Receiver + Level-Shifter 2018年 12月 28日
Application note Glitch free power sequencing with AXC level translators (Rev. A) 2018年 9月 20日
Application note Evaluate SN74AXC1T45DRL Using A Generic EVM 2017年 11月 6日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
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開發板

AVCLVCDIRCNTRL-EVM — 適用於方向控制雙向轉換裝置、支援 AVC 和 LVC 的通用 EVM

通用 EVM 的設計可支援一、二、四、八通道 LVC 及 AVC 方向控制的轉換裝置。此外也支援相同通道數量的匯流排保留與汽車 -Q1 裝置。AVC 是低電壓轉換裝置，具較低驅動強度 12mA。LVC 是較高的電壓轉換裝置，範圍從 1.65 到 5.5V 且具較高驅動強度 32mA。

使用指南: PDF
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模擬型號

SN74AXC1T45 IBIS Model (Rev. A)

SCEM581A.ZIP (51 KB) - IBIS Model
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOT-23 (DBV) 6 Ultra Librarian
SOT-5X3 (DRL) 6 Ultra Librarian
SOT-SC70 (DCK) 6 Ultra Librarian
X2SON (DEA) 6 Ultra Librarian
X2SON (DTQ) 6 Ultra Librarian
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