產品詳細資料

Bits (#) 1 Data rate (max) (Mbps) 420 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.1 Vin (max) (V) 5.5 Vout (min) (V) 1.1 Vout (max) (V) 5.5 Applications GPIO Features Integrated pulldown resistors, Partial power down (Ioff), Vcc disconnect, Vcc isolation Prop delay (ns) 11 Technology family LXC Supply current (max) (mA) 0.004 Rating Catalog Operating temperature range (°C) -40 to 125
Bits (#) 1 Data rate (max) (Mbps) 420 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.1 Vin (max) (V) 5.5 Vout (min) (V) 1.1 Vout (max) (V) 5.5 Applications GPIO Features Integrated pulldown resistors, Partial power down (Ioff), Vcc disconnect, Vcc isolation Prop delay (ns) 11 Technology family LXC Supply current (max) (mA) 0.004 Rating Catalog Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 6 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DTQ) 6 0.8 mm² 1 x 0.8
  • Fully configurable dual-rail design allows each port to operate from 1.1 V to 5.5 V
  • Robust, glitch-free power supply sequencing
  • Up to 420-Mbps support for 3.3 V to 5.0 V
  • Schmitt-trigger inputs allow for slow or noisy inputs
  • I/O’s with integrated dynamic pull-down resistors help reduce external component count
  • Control inputs with integrated static pull-down resistors allow for floating control inputs
  • High drive strength (up to 32 mA at 5 V)
  • Low power consumption
    • 3-µA maximum (25°C)
    • 6-µA maximum (–40°C to 125°C)
  • VCC isolation and Vcc disconnect (Ioff-float) feature
    • If either VCC supply is < 100 mV or disconnected, all I/O’s get pulled-down and then become high-impedance
  • Ioff supports partial-power-down mode operation
  • Compatible with LVC family level shifters
  • Control logic (DIR and OE) are referenced to VCCA
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 4000-V human-body model
    • 1000-V charged-device model
  • Fully configurable dual-rail design allows each port to operate from 1.1 V to 5.5 V
  • Robust, glitch-free power supply sequencing
  • Up to 420-Mbps support for 3.3 V to 5.0 V
  • Schmitt-trigger inputs allow for slow or noisy inputs
  • I/O’s with integrated dynamic pull-down resistors help reduce external component count
  • Control inputs with integrated static pull-down resistors allow for floating control inputs
  • High drive strength (up to 32 mA at 5 V)
  • Low power consumption
    • 3-µA maximum (25°C)
    • 6-µA maximum (–40°C to 125°C)
  • VCC isolation and Vcc disconnect (Ioff-float) feature
    • If either VCC supply is < 100 mV or disconnected, all I/O’s get pulled-down and then become high-impedance
  • Ioff supports partial-power-down mode operation
  • Compatible with LVC family level shifters
  • Control logic (DIR and OE) are referenced to VCCA
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 4000-V human-body model
    • 1000-V charged-device model

The SN74LXC1T45 is a 1-bit, dual-supply noninverting bidirectional voltage level translation device. The I/O pin A and control pin (DIR) are referenced to VCCA logic levels, and the I/O pin B are referenced to VCCB logic levels. The A pin is able to accept I/O voltages ranging from 1.1 V to 5.5 V, while the B pin can accept I/O voltages from 1.1 V to 5.5 V. A high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A. See Device Functional Modes for a summary of the operation of the control logic.

The SN74LXC1T45 is a 1-bit, dual-supply noninverting bidirectional voltage level translation device. The I/O pin A and control pin (DIR) are referenced to VCCA logic levels, and the I/O pin B are referenced to VCCB logic levels. The A pin is able to accept I/O voltages ranging from 1.1 V to 5.5 V, while the B pin can accept I/O voltages from 1.1 V to 5.5 V. A high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A. See Device Functional Modes for a summary of the operation of the control logic.

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類型 標題 日期
* Data sheet SN74LXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Level Shifting datasheet (Rev. A) PDF | HTML 2021年 12月 10日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Application brief Enabling Power-Efficient FPGA Designs With Level Translation PDF | HTML 2024年 4月 30日
Product overview Enabling System on Module Industrial PC Connectivity With Level Translation PDF | HTML 2023年 4月 3日
Application brief Enabling Next Generation Processors, FPGA, and ASSP with Voltage Level Translat PDF | HTML 2023年 1月 17日
Application brief Enabling LED and LCD Indicators in Modern System Designs PDF | HTML 2022年 8月 1日

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開發板

AVCLVCDIRCNTRL-EVM — 適用於方向控制雙向轉換裝置、支援 AVC 和 LVC 的通用 EVM

通用 EVM 的設計可支援一、二、四、八通道 LVC 及 AVC 方向控制的轉換裝置。此外也支援相同通道數量的匯流排保留與汽車 -Q1 裝置。AVC 是低電壓轉換裝置,具較低驅動強度 12mA。LVC 是較高的電壓轉換裝置,範圍從 1.65 到 5.5V 且具較高驅動強度 32mA。

使用指南: PDF
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模擬型號

SN74LXC1T45 IBIS Model

SCEM790.ZIP (56 KB) - IBIS Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOT-23 (DBV) 6 Ultra Librarian
SOT-SC70 (DCK) 6 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DTQ) 6 Ultra Librarian

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