產品詳細資料

Technology family LVC Number of channels 4 IOL (max) (mA) 24 Supply current (max) (µA) 40 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 4 IOL (max) (mA) 24 Supply current (max) (µA) 40 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) SOP (NS) 14 79.56 mm² (10.2 mm × 7.8 mm) SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) VQFN (RGY) 14 12.25 mm² (3.5 mm × 3.5 mm) SSOP (DB) 14 48.36 mm² (6.2 mm × 7.8 mm) WQFN (BQA) 14 7.5 mm² (3 mm × 2.5 mm)
  • 3-State outputs
  • Separate OE for all 4 buffers
  • Operates from 1.65V to 3.6V
  • Specified from –40°C to 85°C and –40°C to 125°C
  • Inputs accept voltages to 5.5V
  • Max tpd of 4.8ns at 3.3V
  • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250mA per JESD 17
  • 3-State outputs
  • Separate OE for all 4 buffers
  • Operates from 1.65V to 3.6V
  • Specified from –40°C to 85°C and –40°C to 125°C
  • Inputs accept voltages to 5.5V
  • Max tpd of 4.8ns at 3.3V
  • Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, TA = 25°C
  • Latch-up performance exceeds 250mA per JESD 17

This quadruple bus buffer gate is designed for 1.65V to 3.6V VCC operation.

The SN74LVC125A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment.

This quadruple bus buffer gate is designed for 1.65V to 3.6V VCC operation.

The SN74LVC125A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74LVC125A Quadruple Bus Buffer Gate With 3-State Outputs datasheet (Rev. T) PDF | HTML 2024/9/6
Application brief Optimizing Optical Network Terminal Units With Logic PDF | HTML 2023/4/5
Application brief Optimizing Board Space for Discrete LOGIC Designs Using Smallest Package Solutio (Rev. A) PDF | HTML 2022/9/29

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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

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14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM),設計用於支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。

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模擬型號

HSPICE Model for SN74LVC125A

SCEJ248.ZIP (97 KB) - HSpice 模型
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SN74LVC125A Behavioral SPICE Model

SCAM111.ZIP (7 KB) - PSpice 模型
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SN74LVC125A IBIS Model (Rev. C)

SCEM013C.ZIP (45 KB) - IBIS 模型
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SN74LVC125A PSpice Transient Model

SCAM059.ZIP (30 KB) - PSpice 模型
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SN74LVC125A TINA-TI Transient Reference Design

SCAM060.ZIP (44 KB) - TINA-TI 參考設計
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SN74LVC125A TINA-TI Transient Spice Model

SCAM061.ZIP (9 KB) - TINA-TI Spice 模型
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參考設計

TIDA-00189 — 隔離迴路供電熱電偶發送器參考設計

隔離迴路供電熱電偶發送器參考設計是一款系統解決方案,為 4 至 20mA 隔離式電流迴路應用提供精密的 K 型熱電偶量測。此設計旨在作為評估模組,供使用者快速建立原型,並開發用於製程控制和工廠自動化的終端產品。作為溫度感測器的熱電偶潛在挑戰包括微小的電壓輸出、低靈敏度和非線性;此外,由於在工業環境中,接地電位差高於 100V 的現象十分常見,因此熱電偶與訊號調節電路必須進行電氣隔離。設計檔案包括設計考量、方塊圖、電路圖、物料清單 (BOM)、層圖、Altium 檔案、Gerber 檔案和 MSP430 韌體。

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
VQFN (RGY) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian

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