產品詳細資料

Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.7 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.4 BW at Acl (MHz) 150 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 220 Architecture Bipolar, Fully Differential ADC Driver Vn at flatband (typ) (nV√Hz) 3.3 Iq per channel (typ) (mA) 1.35 Rail-to-rail In to V-, Out Vos (offset voltage at 25°C) (max) (mV) 0.175 Operating temperature range (°C) -40 to 125 Iout (typ) (mA) 45 2nd harmonic (dBc) 128 3rd harmonic (dBc) 139 Frequency of harmonic distortion measurement (MHz) 0.1 GBW (typ) (MHz) 135 Input bias current (max) (pA) 1500000 Features Shutdown CMRR (typ) (dB) 110 Rating Catalog
Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.7 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.4 BW at Acl (MHz) 150 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 220 Architecture Bipolar, Fully Differential ADC Driver Vn at flatband (typ) (nV√Hz) 3.3 Iq per channel (typ) (mA) 1.35 Rail-to-rail In to V-, Out Vos (offset voltage at 25°C) (max) (mV) 0.175 Operating temperature range (°C) -40 to 125 Iout (typ) (mA) 45 2nd harmonic (dBc) 128 3rd harmonic (dBc) 139 Frequency of harmonic distortion measurement (MHz) 0.1 GBW (typ) (MHz) 135 Input bias current (max) (pA) 1500000 Features Shutdown CMRR (typ) (dB) 110 Rating Catalog
WQFN (RUN) 10 4 mm² (2 mm × 2 mm) VQFN (RGT) 16 9 mm² (3 mm × 3 mm) VSSOP (DGK) 8 14.7 mm² (3 mm × 4.9 mm)
  • Bandwidth: 150 MHz (G = 1 V/V)
  • Differential Output Slew Rate: 220 V/µs
  • Gain Bandwidth Product: 135 MHz
  • Negative Rail Input (NRI), Rail-to-Rail Output (RRO)
  • Wide Output Common-Mode Control Range
  • Single-Supply Operating Range: 2.7 V to 5.4 V
  • Trimmed-Supply Current: 1.37 mA at 5 V
  • 25°C Input Offset: ±175 µV (max)
  • Input Offset Voltage Drift: ±1.8 µV/°C (max)
  • Differential Input Voltage Noise: 3.3 nV/√ Hz
  • HD2: –128 dBc at 2 VPP, 100 kHz
  • HD3: –139 dBc at 2 VPP, 100 kHz
  • < 50-ns Settling Time: 4-V Step to 0.01%
  • 18-Bit Settling Time: 4-V Step, < 500 ns
  • Bandwidth: 150 MHz (G = 1 V/V)
  • Differential Output Slew Rate: 220 V/µs
  • Gain Bandwidth Product: 135 MHz
  • Negative Rail Input (NRI), Rail-to-Rail Output (RRO)
  • Wide Output Common-Mode Control Range
  • Single-Supply Operating Range: 2.7 V to 5.4 V
  • Trimmed-Supply Current: 1.37 mA at 5 V
  • 25°C Input Offset: ±175 µV (max)
  • Input Offset Voltage Drift: ±1.8 µV/°C (max)
  • Differential Input Voltage Noise: 3.3 nV/√ Hz
  • HD2: –128 dBc at 2 VPP, 100 kHz
  • HD3: –139 dBc at 2 VPP, 100 kHz
  • < 50-ns Settling Time: 4-V Step to 0.01%
  • 18-Bit Settling Time: 4-V Step, < 500 ns

The THS4551 fully differential amplifier offers an easy interface from single-ended sources to the differential output required by high-precision analog-to-digital converters (ADCs). Designed for exceptional dc accuracy, low noise, and robust capacitive load driving, this device is well suited for data acquisition systems where high precision is required along with the best signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) through the amplifier and ADC combination.

The THS4551 features the negative rail input required when interfacing a dc-coupled, ground-centered, source signal to a single-supply differential input ADC. Very low dc error and drift terms support the emerging 16- to 20-bit successive-approximation register (SAR) input requirements. A wide-range output common-mode control supports the ADC running from 1.8-V to 5-V supplies with ADC common-mode input requirements from 0.7 V to greater than 3.0 V.

The THS4551 device is characterized for operation over the wide temperature range of –40°C to +125°C, and is available in 8-pin VSSOP, 16-pin VQFN, and 10-pin WQFN packages.

The THS4551 fully differential amplifier offers an easy interface from single-ended sources to the differential output required by high-precision analog-to-digital converters (ADCs). Designed for exceptional dc accuracy, low noise, and robust capacitive load driving, this device is well suited for data acquisition systems where high precision is required along with the best signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) through the amplifier and ADC combination.

The THS4551 features the negative rail input required when interfacing a dc-coupled, ground-centered, source signal to a single-supply differential input ADC. Very low dc error and drift terms support the emerging 16- to 20-bit successive-approximation register (SAR) input requirements. A wide-range output common-mode control supports the ADC running from 1.8-V to 5-V supplies with ADC common-mode input requirements from 0.7 V to greater than 3.0 V.

The THS4551 device is characterized for operation over the wide temperature range of –40°C to +125°C, and is available in 8-pin VSSOP, 16-pin VQFN, and 10-pin WQFN packages.

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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 THS4551 Low-Noise, Precision, 150-MHz, Fully Differential Amplifier datasheet (Rev. D) PDF | HTML 2021/4/23
技術文章 Go Differential to Differentiate Your Precision Design (Rev. A) PDF | HTML 2026/2/10
Application brief Why Use an FDA to Drive an ADC? PDF | HTML 2026/1/8
Application brief Active Filter Design for Differential ADCs (Rev. A) PDF | HTML 2025/10/8
Product overview High Speed Amplifiers for Motor Encoders and Position Sensing PDF | HTML 2025/4/11
Product overview High Speed Amplifiers for In-Vitro Diagnostics (IVD) Analog Front End PDF | HTML 2025/4/10
Circuit design High-input impedance, true differential, AFE attenuator circuit for SAR ADCs (Rev. B) PDF | HTML 2024/9/25
Circuit design True differential, 4 × 2 MUX, analog front end, simultaneous-sampling ADC circui (Rev. B) PDF | HTML 2024/9/20
Circuit design High-current battery monitor circuit: 0–10A, 0-10kHz, 18 bit (Rev. A) PDF | HTML 2024/9/12
應用說明 Continuous Wave Doppler Signal Chain Designs for TI’s Ultrasound AFE (Rev. A) PDF | HTML 2024/5/22
Product overview Pairing ADC Drivers With Fully-Differential Input ADCs for Wide Bandwidth Data Acquisition 2024/4/1
Product overview PLC Analog Input Front-End Architectures PDF | HTML 2022/7/31
技術文章 Balancing ADC size, power, resolution and bandwidth in precision data-acquisition PDF | HTML 2021/12/3
Application brief Optimizing LCR Meter Front-End Design for Accurate Impedance Measurements PDF | HTML 2021/1/20
Application brief Setting a Constant Common-Mode Voltage for Fully-Differential SAR ADC Inputs 2019/9/6
Application brief Maximizing System Total Harmonic Distortion Using High Speed Amplifiers 2018/6/20
應用說明 Attenuator Amplifier Design to Maximize the Input Voltage of Differential ADCs 2018/6/14
應用說明 Precision Sum Circuit Support Hi Output Current Multiple AFEs in Ultasound App 2017/11/20
技術文章 Powering up the performance of sensitive test and measurement systems PDF | HTML 2017/10/17
電子書 The Signal e-book: A compendium of blog posts on op amp design topics PDF | HTML 2017/3/28
技術文章 What you need to know about input bias current – and why PDF | HTML 2016/12/8

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DEM-FDA-RUN-EVM — 採用 WQFN (RUN) 封裝的全差分放大器評估模組

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THS4551DGKEVM — THS4551DGK 評估模組

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THS4551RGTEVM — THS4551RGT 評估模組

THS4551RGTEVM 是一款採用 RGT (WQFN-10) 封裝的評估模組,適用於單 THS4551 放大器。此評估模組可快速且輕鬆展示放大器的功能性和多元用途。EVM 隨時可透過板載連接器來連接電源、訊號源和測試儀器。EVM 已配置為可透過其輸入與輸出,輕鬆連接常見的 50-Ω 實驗室設備。
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THS4551RUNEVM — THS4551RUN 評估模組

THS4551RUNEVM 是一款採用 RUN (WQFN-10) 封裝的評估模組,適用於單 THS4551 放大器。此評估模組可快速且輕鬆展示放大器的功能性和多元用途。EVM 隨時可透過板載連接器來連接電源、訊號源和測試儀器。EVM 已配置為可透過其輸入與輸出,輕鬆連接常見的 50-Ω 實驗室設備。
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SBOC461 — TINA-TI ADS127L01 MFB Driver LG Test of Figure78 THS4551

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SBOC462 — TINA-TI ADS127L01 MFB Driver of Figure78 THS4551

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THS4551 PSpice Model (Rev. B)

SBOMB92B.ZIP (53 KB) - PSpice 模型
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THS4551 TINA-TI Spice Model (Rev. C)

SBOMA28C (7439 KB) - TINA-TI Spice 模型
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THS4551DGK Unencrypted TINA-TI Model Package (Rev. C)

SBOMA29C.TSC (35 KB) - TINA-TI 參考設計
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TINA-TI 100kHz MFB filter LG test of Figure 87 THS4551

SBOC459.ZIP (80 KB) - TINA-TI Spice 模型
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TINA-TI AC coupled different IO Figure 75 THS4551

SLOC341.ZIP (107 KB) - TINA-TI Spice 模型
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TINA-TI AC Coupled Single to Differentiate Gain of 2 Figure70 THS4551

SBOC460.ZIP (147 KB) - TINA-TI Spice 模型
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TINA-TI ADTL1-4-75 Model Test for Figure 62 THS4551

SBOC463.ZIP (198 KB) - TINA-TI Spice 模型
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TINA-TI Attenuator With a Caps Gain of 0.1 Figure81 THS4551

SBOC464.ZIP (199 KB) - TINA-TI Spice 模型
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TINA-TI Attenuator With No Caps Gain of 0.1 Figure80 THS4551

SBOC465.ZIP (201 KB) - TINA-TI Spice 模型
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TINA-TI Basic Gain of 1 Test Circuit Figure61 THS4551

SBOC466.ZIP (228 KB) - TINA-TI Spice 模型
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TINA-TI Common Mode Test CKT Figure65 THS4551

SBOC467.ZIP (118 KB) - TINA-TI Spice 模型
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TINA-TI Differential Audio DAC ZT Design Figure90 THS4551

SBOC468.ZIP (87 KB) - TINA-TI Spice 模型
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TINA-TI Differential IO with OPA2192 to FDA to SAR Figure 76 THS4551

SBOC469.ZIP (118 KB) - TINA-TI Spice 模型
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TINA-TI Differential Transimpedance LG Sim Figure90 THS4551

SBOC470.ZIP (10 KB) - TINA-TI Spice 模型
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TINA-TI Gain of 0.2 100kHz Butterworth MFB Filter Figure87 THS4551

SBOC471.ZIP (171 KB) - TINA-TI Spice 模型
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TINA-TI Gain of 5 Single to Different Simplified for Figure72 THS4551

SBOC472.ZIP (89 KB) - TINA-TI Spice 模型
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TINA-TI Gain of 5 Single to Different with 10Mhz Bessel Figure93 THS4551

SBOC473.ZIP (218 KB) - TINA-TI Spice 模型
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TINA-TI High Gain Single to Different with Feedback Pole and Input C Figure 85

SBOC474.ZIP (101 KB) - TINA-TI Spice 模型
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TINA-TI High Gain Single to Different with Feedback Pole Figure 83 THS4551

SBOC475.ZIP (117 KB) - TINA-TI Spice 模型
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TINA-TI Open Loop No Load Response Figure99 THS4551

SBOC476.ZIP (68 KB) - TINA-TI Spice 模型
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TINA-TI Single to Differential Attenuator Figure71 THS4551

SBOC477.ZIP (119 KB) - TINA-TI Spice 模型
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計算工具

SBOR022 — TI FDA Calculator

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許多 TI 參考設計包含 THS4551

使用我們的參考設計選擇工具,以檢視並找出最適合您的應用和參數的設計。

封裝 針腳 CAD 符號、佔位空間與 3D 模型
WQFN (RUN) 10 Ultra Librarian
VQFN (RGT) 16 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian

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