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THS4552

現行

雙通道、低雜訊、精密、150-MHz、全差分放大器

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產品規格表

THS4552

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 2 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.7 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.4 BW at Acl (MHz) 150 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 220 Architecture Bipolar, Fully Differential ADC Driver Vn at flatband (typ) (nV√Hz) 3.3 Iq per channel (typ) (mA) 1.37 Rail-to-rail In to V-, Out Vos (offset voltage at 25°C) (max) (mV) 0.265 Operating temperature range (°C) -40 to 125 Iout (typ) (mA) 65 2nd harmonic (dBc) 128 3rd harmonic (dBc) 139 Frequency of harmonic distortion measurement (MHz) 0.1 GBW (typ) (MHz) 135 Input bias current (max) (pA) 1500000 Features Shutdown CMRR (typ) (dB) 110 Rating Catalog
Number of channels 2 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.7 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.4 BW at Acl (MHz) 150 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 220 Architecture Bipolar, Fully Differential ADC Driver Vn at flatband (typ) (nV√Hz) 3.3 Iq per channel (typ) (mA) 1.37 Rail-to-rail In to V-, Out Vos (offset voltage at 25°C) (max) (mV) 0.265 Operating temperature range (°C) -40 to 125 Iout (typ) (mA) 65 2nd harmonic (dBc) 128 3rd harmonic (dBc) 139 Frequency of harmonic distortion measurement (MHz) 0.1 GBW (typ) (MHz) 135 Input bias current (max) (pA) 1500000 Features Shutdown CMRR (typ) (dB) 110 Rating Catalog
WQFN (RTW) 24 16 mm² (4 mm × 4 mm) TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm)
  • Bandwidth: 150 MHz (G = 1 V/V)
  • Differential output slew rate: 220 V/µs
  • Gain bandwidth product: 135 MHz
  • Negative rail input (NRI), rail-to-rail output (RRO)
  • Wide output common-mode control range
  • Single-supply operating range: 2.7 V to 5.4 V
  • Trimmed-supply current: 1.37 mA per channel at 5 V
  • 25°C input offset: ±175 µV (maximum)
  • Input offset voltage drift: ±2.0 µV/°C (maximum)
  • Differential input voltage noise: 3.3 nV/√ Hz
  • HD2: –128 dBc at 2 VPP, 100 kHz
  • HD3: –139 dBc at 2 VPP, 100 kHz
  • < 50 ns settling time: 4 V Step to 0.01%
  • 18-bit settling time: 4 V Step, < 500 ns
  • Bandwidth: 150 MHz (G = 1 V/V)
  • Differential output slew rate: 220 V/µs
  • Gain bandwidth product: 135 MHz
  • Negative rail input (NRI), rail-to-rail output (RRO)
  • Wide output common-mode control range
  • Single-supply operating range: 2.7 V to 5.4 V
  • Trimmed-supply current: 1.37 mA per channel at 5 V
  • 25°C input offset: ±175 µV (maximum)
  • Input offset voltage drift: ±2.0 µV/°C (maximum)
  • Differential input voltage noise: 3.3 nV/√ Hz
  • HD2: –128 dBc at 2 VPP, 100 kHz
  • HD3: –139 dBc at 2 VPP, 100 kHz
  • < 50 ns settling time: 4 V Step to 0.01%
  • 18-bit settling time: 4 V Step, < 500 ns

The THS4552 fully differential amplifier offers an easy interface from single-ended sources to the differential output required by high-precision analog-to-digital converters (ADCs). Designed for exceptional dc accuracy, low noise, and robust capacitive load driving, this device is well suited for data acquisition systems where high precision is required along with the best signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) through the amplifier and ADC combination.

The THS4552 features the negative rail input required when interfacing a dc-coupled, ground-centered, source signal to a single-supply differential input ADC. Very low dc error and drift terms support the emerging 16- to 20-bit successive-approximation register (SAR) input requirements. A wide-range output common-mode control supports the ADC running from 1.8 V to 5 V supplies with ADC common-mode input requirements from 0.7 V to greater than 3.0 V.

The THS4552 device is characterized for operation over the wide temperature range of –40°C to +125°C, and is available in 16-pin TSSOP and 24-pin VQFN packages.

The THS4552 fully differential amplifier offers an easy interface from single-ended sources to the differential output required by high-precision analog-to-digital converters (ADCs). Designed for exceptional dc accuracy, low noise, and robust capacitive load driving, this device is well suited for data acquisition systems where high precision is required along with the best signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) through the amplifier and ADC combination.

The THS4552 features the negative rail input required when interfacing a dc-coupled, ground-centered, source signal to a single-supply differential input ADC. Very low dc error and drift terms support the emerging 16- to 20-bit successive-approximation register (SAR) input requirements. A wide-range output common-mode control supports the ADC running from 1.8 V to 5 V supplies with ADC common-mode input requirements from 0.7 V to greater than 3.0 V.

The THS4552 device is characterized for operation over the wide temperature range of –40°C to +125°C, and is available in 16-pin TSSOP and 24-pin VQFN packages.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 THS4552 Dual-Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier datasheet (Rev. B) PDF | HTML 2021/6/16
Application brief Why Use an FDA to Drive an ADC? PDF | HTML 2026/1/8
Application brief Active Filter Design for Differential ADCs (Rev. A) PDF | HTML 2025/10/8
Circuit design Single-ended input to differential output circuit using a fully-differential amp (Rev. A) PDF | HTML 2024/9/25
應用說明 Continuous Wave Doppler Signal Chain Designs for TI’s Ultrasound AFE (Rev. A) PDF | HTML 2024/5/22
電子書 Engineer's Guide to High-Speed Amplifiers PDF | HTML 2023/10/18
應用說明 Attenuator Amplifier Design to Maximize the Input Voltage of Differential ADCs 2018/6/14
電子書 The Signal e-book: A compendium of blog posts on op amp design topics PDF | HTML 2017/3/28
類比設計期刊 Using single-supply fully diff. amps with neg. input voltages to drive ADCs 2010/11/15

設計與開發

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開發板

THS4552PWEVM — THS4552PW 評估模組

THS4552PWEVM 是一款採用 PW（16 針腳 TSSOP）封裝的雙 THS4552 放大器評估模組。此評估模組可快速且輕鬆展示放大器的功能性和多元用途。EVM 隨時可透過板載連接器來連接電源、訊號源和測試儀器。EVM 已配置為可透過其輸入與輸出，輕鬆連接常見的 50-Ω 實驗室設備。
使用指南: PDF
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THS4552RTWEVM — THS4552RTW 評估模組

THS4552PWEVM 是一款採用 RTW (24 針腳 VQFN) 封裝的雙 THS4552 放大器評估模組。此評估模組可快速且輕鬆展示放大器的功能性和多元用途。EVM 隨時可透過板載連接器來連接電源、訊號源和測試儀器。EVM 已配置為可透過其輸入與輸出，輕鬆連接常見的 50-Ω 實驗室設備。
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SBOC461 — TINA-TI ADS127L01 MFB Driver LG Test of Figure78 THS4551

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SBOC462 — TINA-TI ADS127L01 MFB Driver of Figure78 THS4551

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模擬型號

TINA-TI 100kHz MFB filter LG test of Figure 87 THS4551

SBOC459.ZIP (80 KB) - TINA-TI Spice 模型
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TINA-TI AC Coupled Single to Differentiate Gain of 2 Figure70 THS4551

SBOC460.ZIP (147 KB) - TINA-TI Spice 模型
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TINA-TI ADTL1-4-75 Model Test for Figure 62 THS4551

SBOC463.ZIP (198 KB) - TINA-TI Spice 模型
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TINA-TI Attenuator With a Caps Gain of 0.1 Figure81 THS4551

SBOC464.ZIP (199 KB) - TINA-TI Spice 模型
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TINA-TI Attenuator With No Caps Gain of 0.1 Figure80 THS4551

SBOC465.ZIP (201 KB) - TINA-TI Spice 模型
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TINA-TI Basic Gain of 1 Test Circuit Figure61 THS4551

SBOC466.ZIP (228 KB) - TINA-TI Spice 模型
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TINA-TI Common Mode Test CKT Figure65 THS4551

SBOC467.ZIP (118 KB) - TINA-TI Spice 模型
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TINA-TI Differential Audio DAC ZT Design Figure90 THS4551

SBOC468.ZIP (87 KB) - TINA-TI Spice 模型
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TINA-TI Differential IO with OPA2192 to FDA to SAR Figure 76 THS4551

SBOC469.ZIP (118 KB) - TINA-TI Spice 模型
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TINA-TI Differential Transimpedance LG Sim Figure90 THS4551

SBOC470.ZIP (10 KB) - TINA-TI Spice 模型
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TINA-TI Gain of 0.2 100kHz Butterworth MFB Filter Figure87 THS4551

SBOC471.ZIP (171 KB) - TINA-TI Spice 模型
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TINA-TI Gain of 5 Single to Different Simplified for Figure72 THS4551

SBOC472.ZIP (89 KB) - TINA-TI Spice 模型
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TINA-TI Gain of 5 Single to Different with 10Mhz Bessel Figure93 THS4551

SBOC473.ZIP (218 KB) - TINA-TI Spice 模型
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TINA-TI High Gain Single to Different with Feedback Pole and Input C Figure 85

SBOC474.ZIP (101 KB) - TINA-TI Spice 模型
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TINA-TI High Gain Single to Different with Feedback Pole Figure 83 THS4551

SBOC475.ZIP (117 KB) - TINA-TI Spice 模型
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TINA-TI Open Loop No Load Response Figure99 THS4551

SBOC476.ZIP (68 KB) - TINA-TI Spice 模型
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TINA-TI Single to Differential Attenuator Figure71 THS4551

SBOC477.ZIP (119 KB) - TINA-TI Spice 模型
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計算工具

SBOR022 — TI FDA Calculator

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參考設計

TIDA-010962 — 自動測試設備 (ATE) 80V 離散式浮動 VI 參考設計

此參考設計展現四象限離散式浮動電壓與電流 (VI) 設計。電壓輸出支援 ±40V 和 0V 至 80V 範圍，並提供 500mA、10mA 和 10μA 三種電流範圍。此設計可在強制電壓 (FV)、強制電流 (FI)、緩衝器及具有類比回饋迴路的 Gang 模式下運作。憑藉 20 位元強制數位轉類比轉換器 (DAC) 和 18 位元、2 通道類比轉數位轉換器 (ADC) 以及精密訊號鏈，該參考設計可實現校準後控制與測量具備 0.01% 準確度。

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
WQFN (RTW) 24 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
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