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TLV1812

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雙路微功耗高電壓比較器

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產品規格表

TLV1812

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 2 Output type Push-Pull Propagation delay time (µs) 0.42 Vs (max) (V) 40 Vs (min) (V) 2.4 Vos (offset voltage at 25°C) (max) (mV) 4 Iq per channel (typ) (mA) 0.005 Input bias current (±) (max) (nA) 1.2 Rail-to-rail In Rating Catalog Operating temperature range (°C) -40 to 125 Features POR VICR (max) (V) 40.2 VICR (min) (V) -0.2 TI functional safety category Functional Safety-Capable
Number of channels 2 Output type Push-Pull Propagation delay time (µs) 0.42 Vs (max) (V) 40 Vs (min) (V) 2.4 Vos (offset voltage at 25°C) (max) (mV) 4 Iq per channel (typ) (mA) 0.005 Input bias current (±) (max) (nA) 1.2 Rail-to-rail In Rating Catalog Operating temperature range (°C) -40 to 125 Features POR VICR (max) (V) 40.2 VICR (min) (V) -0.2 TI functional safety category Functional Safety-Capable
SOIC (D) 8 29.4 mm² 4.9 x 6 SOT-23-THN (DDF) 8 8.12 mm² 2.9 x 2.8 TSSOP (PW) 8 19.2 mm² 3 x 6.4 VSSOP (DGK) 8 14.7 mm² 3 x 4.9 WSON (DSG) 8 4 mm² 2 x 2
  • Wide 2.4 V to 40 V supply range
  • Rail-to-rail input
  • Power-On Reset (POR) for known start-up
  • Low input offset voltage 500 µV
  • 420ns typical propagation delay
  • Low quiescent current 5 µA per channel
  • Low input bias current 150 fA
  • Open-drain output option (TLV182x)
  • Push-pull output option (TLV181x)
  • Full -40°C to +125°C temperature range
  • 2 kV ESD protection
  • Functional Safety-Capable
  • Wide 2.4 V to 40 V supply range
  • Rail-to-rail input
  • Power-On Reset (POR) for known start-up
  • Low input offset voltage 500 µV
  • 420ns typical propagation delay
  • Low quiescent current 5 µA per channel
  • Low input bias current 150 fA
  • Open-drain output option (TLV182x)
  • Push-pull output option (TLV181x)
  • Full -40°C to +125°C temperature range
  • 2 kV ESD protection
  • Functional Safety-Capable

The TLV181x and TLV182x are a family of 40 Volt single, dual and quad channel comparators with multiple output options. The family offers rail-to-rail inputs with push-pull or open-drain output options. The family has an excellent speed-to-power combination with a propagation delay of 420 ns with a full supply voltage range of 2.4 V to 40 V with a quiescent supply current of only 5 µA per channel.

All devices include a Power-On Reset (POR) feature. This makes sure the output is in a known state until the minimum supply voltage has been reached before the output responds to the inputs, thus preventing false outputs during system power-up and power-down.

The TLV181x comparators have a push-pull output stage capable of sinking and sourcing milliamps of current when controlling an LED or driving a capacitive load such as a MOSFET gate.

The TLV182x comparators have an open-drain output stage that can be pulled up to 40 V independent of comparator supply voltage.

The TLV181x and TLV182x are a family of 40 Volt single, dual and quad channel comparators with multiple output options. The family offers rail-to-rail inputs with push-pull or open-drain output options. The family has an excellent speed-to-power combination with a propagation delay of 420 ns with a full supply voltage range of 2.4 V to 40 V with a quiescent supply current of only 5 µA per channel.

All devices include a Power-On Reset (POR) feature. This makes sure the output is in a known state until the minimum supply voltage has been reached before the output responds to the inputs, thus preventing false outputs during system power-up and power-down.

The TLV181x comparators have a push-pull output stage capable of sinking and sourcing milliamps of current when controlling an LED or driving a capacitive load such as a MOSFET gate.

The TLV182x comparators have an open-drain output stage that can be pulled up to 40 V independent of comparator supply voltage.
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類型 標題 日期
* Data sheet TLV181x and TLV182x Family of 40 V Rail-to-Rail Input Comparators with Push-Pull or Open-Drain Output Options datasheet (Rev. C) PDF | HTML 2023年 9月 6日
Application note Comparator Input Types PDF | HTML 2023年 2月 7日
Functional safety information TLV1812, TLV1822 Functional Safety, FIT Rate, Failure Mode Dist, and Pin FMA PDF | HTML 2022年 9月 23日

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TLV181x PSpice Model (Rev. A)

SNOM762A.ZIP (1571 KB) - PSpice Model
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TLV181x TINA-TI Spice Model

SNOM759.ZIP (10 KB) - TINA-TI Spice Model
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — 基於 SPICE 的類比模擬程式

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封裝 引腳 下載
SOIC (D) 8 檢視選項
SOT-23-THN (DDF) 8 檢視選項
TSSOP (PW) 8 檢視選項
VSSOP (DGK) 8 檢視選項
WSON (DSG) 8 檢視選項
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