TLV2548M
- Maximum Throughput 200-KSPS
- Built-In Reference, Conversion Clock and 8× FIFO
- Differential/Integral Nonlinearity Error:
±1.2 LSB at –55°C to 125°C - Signal-to-Noise and Distortion Ratio:
65 dB, fi = 12-kHz at –55°C to 125°C - Spurious Free Dynamic Range: 75 dB, fi = 12- kHz
- SPI/DSP-Compatible Serial Interfaces With SCLK up to 20-MHz
- Single Wide Range Supply 3 Vdc to 5.5 Vdc
- Analog Input Range 0-V to Supply Voltage With 500 kHz BW
- Hardware Controlled and Programmable Sampling Period
- Low Operating Current (1-mA at 3.3-V, 2-mA at 5.5-V With External Ref,
1.7-mA at 3.3-V, 2.4-mA at 5.5-V With Internal Ref) - Power Down: Software/Hardware Power-Down Mode (1 µA Typ, Ext Ref),
Autopower-Down Mode (1 µA Typ, Ext Ref) - Programmable Auto-Channel Sweep
- Available in Q-Temp Automotive High Reliability Automotive Applications
Configuration Control/Print Support Qualification to Automotive Standards
The TLV2544Q, TLV2548Q, and TLV2548M are a family of high performance, 12-bit low power, 3.5 µs, CMOS analog-to-digital converters (ADC) which operate from a single 3-V to 5.5-V power supply. These devices have three digital inputs and a 3-state output [chip select (CS), serial input-output clock (SCLK), serial data input (SDI), and serial data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced with a DSP, a frame sync (FS) signal is used to indicate the start of a serial data frame.
In addition to a high-speed A/D converter and versatile control capability, these devices have an on-chip analog multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special pin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short (12 SCLKs) or as long (24 SCLKs) to accommodate faster SCLK operation popular among high-performance signal processors. The TLV2548 and TLV2544 are designed to operate with very low power consumption. The power-saving feature is further enhanced with software/hardware/autopower-down modes and programmable conversion speeds. The conversion clock (OSC) and reference are built-in. The converter can use the external SCLK as the source of the conversion clock to achieve higher (up to 2.8 µs when a 20 MHz SCLK is used) conversion speed. Two different internal reference voltages are available. An optional external reference can also be used to achieve maximum flexibility.
The TLV2544Q and the TLV2548Q are characterized for operation from –40°C to 125°C. The TLV2548M is characterized for operation from –55°C to 125°C.
您可能會感興趣的類似產品
功能相似於所比較的產品。
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | 3-V to 5.5-V, 12-Bit, 200-KSPS, 4-/8-Channel, Low-Power Serial Analog-to-Digital datasheet (Rev. F) | 2009/10/7 | |||
| * | SMD | TLV2548M SMD 5962-99570 | 2016/6/21 | |||
| 電子書 | Best of Baker's Best: Precision Data Converters -- SAR ADCs | 2015/5/21 | ||||
| 應用說明 | Determining Minimum Acquisition Times for SAR ADCs, part 2 | 2011/3/17 | ||||
| 應用說明 | Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A) | 2010/11/10 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| LCCC (FK) | 20 | Ultra Librarian |