TMS320C6412

現行

C64x 定點 DSP - 高達 720MHz、McBSP、McASP、I2cC、乙太網路

立即訂購

產品規格表

document-pdfAcrobat TMS320C6412 Fixed-Point Digital Signal Processor datasheet (Rev. J) (英文)

TMS320C6412

現行

產品規格表

立即訂購

產品詳細資料

CPU

32-/64-bit

Frequency (MHz)

500, 600, 720

PCIe

1 PCI

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

-40 to 105

CPU

32-/64-bit

Frequency (MHz)

500, 600, 720

PCIe

1 PCI

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

-40 to 105

OMFCBGA (GDK)

548

529 mm² (23 mm × 23 mm)

OMFCBGA (ZDK)

548

529 mm² (23 mm × 23 mm)

OMFCBGA (ZNZ)

548

729 mm² (27 mm × 27 mm)

High-Performance Digital Media Processor (TMS320C6412)
- 2-, 1.67-, 1.39-ns Instruction Cycle Time
- 500-, 600-, 720-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 4000, 4800, 5760 MIPS
- Fully Software-Compatible With C64x™
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
  - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2™ Increased Orthogonality
L1/L2 Memory Architecture
- 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
- 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
- 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
Endianess: Little Endian, Big Endian
64-Bit External Memory Interface (EMIF)
- Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
- 1024M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
10/100 Mb/s Ethernet MAC (EMAC)
- IEEE 802.3 Compliant
- Media Independent Interface (MII)
- 8 Independent Transmit (TX) and 1 Receive (RX) Channel
Management Data Input/Output (MDIO)
Host-Port Interface (HPI) [32-/16-Bit]
32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
Inter-Integrated Circuit (I²C) Bus
Two Multichannel Buffered Serial Ports
Three 32-Bit General-Purpose Timers
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V Internal (-500)
3.3-V I/Os, 1.4-V Internal (A-500, -600, -720)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.

High-Performance Digital Media Processor (TMS320C6412)
- 2-, 1.67-, 1.39-ns Instruction Cycle Time
- 500-, 600-, 720-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 4000, 4800, 5760 MIPS
- Fully Software-Compatible With C64x™
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
  - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2™ Increased Orthogonality
L1/L2 Memory Architecture
- 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
- 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
- 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
Endianess: Little Endian, Big Endian
64-Bit External Memory Interface (EMIF)
- Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
- 1024M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
10/100 Mb/s Ethernet MAC (EMAC)
- IEEE 802.3 Compliant
- Media Independent Interface (MII)
- 8 Independent Transmit (TX) and 1 Receive (RX) Channel
Management Data Input/Output (MDIO)
Host-Port Interface (HPI) [32-/16-Bit]
32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
Inter-Integrated Circuit (I²C) Bus
Two Multichannel Buffered Serial Ports
Three 32-Bit General-Purpose Timers
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V Internal (-500)
3.3-V I/Os, 1.4-V Internal (A-500, -600, -720)

The TMS320C64x™DSPs (including the TMS320C6412 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6412 (C6412) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C6412 device offers cost-effective solutions to high-performance DSP programming challenges. The C6412 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in applications and extend the parallelism of the VelociTI™ architecture. The C6412 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6412 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6412 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a- 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The ethernet media access controller (EMAC) provides an efficient interface between the C6412 DSP core processor and the network. The C6412 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The C6412 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO port, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320C6412 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6412 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

filter

尋找其它音訊與雷達 DSP SoC

下載觀看有字幕稿的影片影片

TI 不提供設計支援

此產品沒有 TI 針對新專案提供的持續設計支援，例如新內容或軟體更新。若有提供，您可在產品資料夾中找到相關資訊、軟體與工具。您也可以在 TI E2E^TM 支援論壇中搜尋封存的資訊。

技術文件

找不到結果。請清除您的搜尋條件，然後再試一次。

檢視所有 63

重要文件	類型	標題	格式選項	日期
*	資料表	TMS320C6412 Fixed-Point Digital Signal Processor datasheet (Rev. J)		2010/10/12
*	勘誤表	TMS320C641x, TMS320DM64x, TMS320DRA342 ZTS, ZNZ, ZDK Packages Discontinued and Converted	PDF \| HTML	2026/2/9
*	勘誤表	TMS320C6412 DSP Silicon Errata (Silicon Revisions 2.0, 1.2, 1.1, 1.0) (Rev. J)		2010/2/4
	應用說明	How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)	PDF \| HTML	2021/5/19
	使用指南	Emulation and Trace Headers Technical Reference Manual (Rev. I)		2012/8/9
	應用說明	Introduction to TMS320C6000 DSP Optimization		2011/10/6
	使用指南	TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J)		2010/7/30
	使用指南	TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q)		2009/7/2
	應用說明	TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)		2007/9/4
	應用說明	Thermal Considerations for the DM64xx, DM64x, and C6000 Devices		2007/5/20
	使用指南	TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E)		2007/4/11
	Product overview	TMS320C6000 DSP TCP/IP Stack Software (Rev. C)		2007/4/4
	使用指南	TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D)		2007/3/26
	使用指南	TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (Rev. C)		2007/1/25
	使用指南	TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G)		2006/12/14
	使用指南	TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C)		2006/11/15
	使用指南	TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C)		2006/2/28
	使用指南	TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C)		2006/1/1
	應用說明	TMS320C6412 Hardware Designer's Resource Guide (Rev. A)		2005/10/21
	應用說明	Migrating from TMS320C64x to TMS320C64x+ (Rev. A)		2005/10/20
	使用指南	TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C)		2005/3/1
	應用說明	TMS320C6412 Power Consumption Summary (Rev. E)		2005/1/27
	使用指南	TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B)		2005/1/25
	應用說明	Use and Handling of Semiconductor Packages With ENIG Pad Finishes		2004/8/31
	使用指南	TMS320C6000 Chip Support Library API Reference Guide (Rev. J)		2004/8/13
	應用說明	TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)		2004/4/26
	應用說明	TMS320C6000 Board Design: Considerations for Debug (Rev. C)		2004/4/21
	使用指南	TMS320C6000 DSP EMAC/MDIO Module Reference Guide (Rev. A)		2004/3/26
	使用指南	TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A)		2004/3/25
	應用說明	TMS320C6000 McBSP Initialization (Rev. C)		2004/3/8
	應用說明	TMS320C64x EDMA Performance Data		2004/3/5
	應用說明	TMS320C6000 EDMA IO Scheduling and Performance		2004/3/5
	應用說明	TMS320C64x EDMA Architecture		2004/3/3
	應用說明	TMS320C64x DSP Peripheral Component Interconnect (PCI) Performance		2003/10/31
	應用說明	TMS320C64x DSP Host Port Interface (HPI) Performance		2003/10/24
	使用指南	TMS320C6000 DSP Designing for JTAG Emulation Reference Guide		2003/7/31
	使用指南	TMS320C6000 DSP Cache User's Guide (Rev. A)		2003/5/5
	應用說明	Using IBIS Models for Timing Analysis (Rev. A)		2003/4/15
	應用說明	TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)		2002/6/4
	應用說明	TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C)		2002/4/17
	應用說明	TMS320C6000 Board Design for JTAG (Rev. C)		2002/4/2
	應用說明	TMS320C6000 EMIF to External Flash Memory (Rev. A)		2002/2/13
	應用說明	Cache Usage in High-Performance DSP Applications with the TMS320C64x		2001/12/13
	應用說明	Using a TMS320C6000 McBSP for Data Packing (Rev. A)		2001/10/31
	應用說明	TMS320C6000 Enhanced DMA: Example Applications (Rev. A)		2001/10/24
	應用說明	Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A)		2001/9/30
	應用說明	TMS320C6000 Host Port to MC68360 Interface (Rev. A)		2001/9/30
	應用說明	Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)		2001/8/31
	應用說明	TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)		2001/8/31
	應用說明	TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)		2001/8/31
	應用說明	TMS320C6000 System Clock Circuit Example (Rev. A)		2001/8/15
	應用說明	TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)		2001/7/23
	應用說明	TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)		2001/7/10
	應用說明	TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)		2001/6/30
	應用說明	TMS320C6000 Host Port to MPC860 Interface (Rev. A)		2001/6/21
	應用說明	TMS320C6000 McBSP: IOM-2 Interface (Rev. A)		2001/5/21
	使用指南	TMS320C64x Technical Overview (Rev. B)		2001/1/30
	應用說明	Circular Buffering on TMS320C6000 (Rev. A)		2000/9/12
	應用說明	TMS320C6000 McBSP as a TDM Highway (Rev. A)		2000/9/11
	應用說明	TMS320C6000 u-Law and a-Law Companding with Software or the McBSP		2000/2/2
	應用說明	General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point		2000/1/31
	應用說明	TMS320C6000 C Compiler: C Implementation of Intrinsics		1999/12/7
	應用說明	TMS320C6000 McBSP: I2S Interface		1999/9/8

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

偵錯探測器

TMDSEMU560V2STM-U — XDS560™ 軟體 v2 系統追蹤 USB 偵錯探測器

XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。請注意，其不支援序列線偵錯 (SWD)。

所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)

支援產品和硬體

有庫存

限制：

登入以進行訂購

lock

登入以檢視庫存

??asset.out-of-stock-ti_zh_TW??

無法提供

偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

支援產品和硬體

有庫存

限制：

登入以進行訂購

lock

登入以檢視庫存

??asset.out-of-stock-ti_zh_TW??

無法提供

偵錯探測器

LB-3P-TRACE32-DSP — 適用於數位訊號處理器 (DSP) 的 Lauterbach TRACE32 偵錯和追蹤系統

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

從：Lauterbach GmbH

支援產品和硬體

檢視選項

IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

支援產品和硬體

啟動

下載選項

驅動程式或資料庫

SPRC090 — Download TMS320C6000 Chip Support Library

晶片支援函式庫 (CSL) 提供了應用程式編程介面 (API)，可用來設定與控制 DSP 晶片內建的周邊設備，以實現易用性、各種 C6000 裝置間的相容性以及硬體抽象。透過提供標準化和可移植性，可縮短開發時間。特性部分列出的函式專門針對下列裝置進行了最佳化：C6201、C6202、C6203、C6204、C6205、C6211、C6410、C6412、C6413、C6414、C6415 、C6416、C6418、C6701、C6711、C6712、C6713、DA610、DM640、DM641 和 DM642。

特色

模組名稱	週邊設備說明
快取	快取
DAT	獨立於裝置的數據複製/填充
DMA	(...)

支援產品和硬體

下載選項

驅動程式或資料庫

SPRC122 — C62x/C64x Fast Run-Time Support Library

C62x/64x FastRTS 庫是一款經過最佳化的浮點函式庫，適用於使用 TMS320C62x 或 TMS320C64x 裝置的 C 編程人員。這些常式通常用於計算密集型即時應用，在這些應用中，最佳執行速度至關重要。透過將當前的浮點庫 (RTS) 函式替換為 FastRTS 函式庫，您無需重寫現有的程式碼，即可顯著提高執行速度。

該版本還包括用於 FastRTS 庫提供的函式子集的 C 語言實作。C 程式碼允許使用者內嵌這些函式並獲得顯著改進的性能。

特色

單精度和雙精度數學函式	單精度和雙精度轉換函式
浮點加法	浮點數轉換為 32 位元有號整數
32 位元有號整數轉換為浮點數
浮點除法	浮點數轉換為 (...)

支援產品和硬體

下載選項

驅動程式或資料庫

SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)

C5000 6000 影像處理庫 (IMGLIB) 是適合 C 程式設計工具的最佳化影像/影片處理函式庫。此函式庫包括 C 可呼叫通用影像/影片處理常式，這些常式通常用於運算密集型即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。IMGLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

支援產品和硬體

檢視選項

驅動程式或資料庫

SPRC265 — TMS320C6000 DSP 函式庫 (DSPLIB)

TMS320C6000 數位訊號處理器函式庫 (DSPLIB) 是適合 C 編程人員的平台最佳化 DSP 函式庫。此函式庫包括可呼叫 C 語言的通用訊號處理常式，通常用於運算密集的即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。DSPLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

支援產品和硬體

檢視選項

驅動程式或資料庫

TELECOMLIB — 電信和媒體庫 - 用於 TMS320C64x+ 和 TMS320C55x 處理器的 FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支援產品和硬體

檢視選項

軟體轉碼器

ADT-3P-DSPVOIPCODECS — 適應性數位技術 DSP VOIP、語音和音訊轉碼器

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)

從：Adaptive Digital Technologies, Inc.

支援產品和硬體

檢視選項

模擬型號