TMS320C6701

現行

C67x 浮點 DSP - 高達 167MHz、McBSP

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產品規格表

document-pdfAcrobat TMS320C6701 Floating-Point DSP datasheet (Rev. F) (英文)

TMS320C6701

現行

立即訂購

產品詳細資料

CPU

32-/64-bit

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

-40 to 105

CPU

32-/64-bit

Operating system

DSP/BIOS

Rating

Catalog

Operating temperature range (°C)

-40 to 105

FCBGA (GJC)

352

1225 mm² (35 mm × 35 mm)

Highest Performance Floating-Point Digital Signal Processor (DSP) TMS320C6701
- 8.3-, 6.7-, 6-ns Instruction Cycle Time
- 120-, 150-, 167-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 1 GFLOPS
- TMS320C6201 Fixed-Point DSP Pin-Compatible
VelociTI™ Advanced Very Long Instruction Word (VLIW) C67x™ CPU Core
- Eight Highly Independent Functional Units:
  - Four ALUs (Floating- and Fixed-Point)
  - Two ALUs (Fixed-Point)
  - Two Multipliers (Floating- and Fixed-Point)
- Load-Store Architecture With 32 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Hardware Support for IEEE Single-Precision Instructions
- Hardware Support for IEEE Double-Precision Instructions
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
1M-Bit On-Chip SRAM
- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
- 512K-Bit Dual-Access Internal Data (64K Bytes)
32-Bit External Memory Interface (EMIF) to Synchronous/Asynchronous Memories
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- 52M-Byte Addressable External Memory Space
Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
16-Bit Host-Port Interface (HPI)
- Access to Entire Memory Map
Two Multichannel Buffered Serial Ports (McBSPs)
- Direct Interface to T1/E1, MVIP, SCSA Framers
- ST-Bus-Switching Compatible
- Up to 256 Channels Each
- AC97-Compatible
- Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock Generator
IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
352-Pin Ball Grid Array (BGA) Package (GJC Suffix)
0.18-µm/5-Level Metal Process
- CMOS Technology
3.3-V I/Os, 1.8-V Internal (120-, 150-MHz)
3.3-V I/Os, 1.9-V Internal (167-MHz Only)

VelociTI is a trademark of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of Microsoft Corporation.

Highest Performance Floating-Point Digital Signal Processor (DSP) TMS320C6701
- 8.3-, 6.7-, 6-ns Instruction Cycle Time
- 120-, 150-, 167-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 1 GFLOPS
- TMS320C6201 Fixed-Point DSP Pin-Compatible
VelociTI™ Advanced Very Long Instruction Word (VLIW) C67x™ CPU Core
- Eight Highly Independent Functional Units:
  - Four ALUs (Floating- and Fixed-Point)
  - Two ALUs (Fixed-Point)
  - Two Multipliers (Floating- and Fixed-Point)
- Load-Store Architecture With 32 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Hardware Support for IEEE Single-Precision Instructions
- Hardware Support for IEEE Double-Precision Instructions
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
1M-Bit On-Chip SRAM
- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
- 512K-Bit Dual-Access Internal Data (64K Bytes)
32-Bit External Memory Interface (EMIF) to Synchronous/Asynchronous Memories
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- 52M-Byte Addressable External Memory Space
Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
16-Bit Host-Port Interface (HPI)
- Access to Entire Memory Map
Two Multichannel Buffered Serial Ports (McBSPs)
- Direct Interface to T1/E1, MVIP, SCSA Framers
- ST-Bus-Switching Compatible
- Up to 256 Channels Each
- AC97-Compatible
- Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock Generator
IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
352-Pin Ball Grid Array (BGA) Package (GJC Suffix)
0.18-µm/5-Level Metal Process
- CMOS Technology
3.3-V I/Os, 1.8-V Internal (120-, 150-MHz)
3.3-V I/Os, 1.9-V Internal (167-MHz Only)

The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000™ DSP platform. The TMS320C6701 (C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the C6701 offers cost-effective solutions to high-performance DSP programming challenges. The C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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重要文件	類型	標題	格式選項
*	資料表	TMS320C6701 Floating-Point DSP datasheet (Rev. F)		2004/3/1
*	勘誤表	TMS320C6701 Silicon Errata (Rev. A)		2001/1/31
	應用說明	How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)	PDF \| HTML	2021/5/19
	應用說明	Introduction to TMS320C6000 DSP Optimization		2011/10/6
	使用指南	TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q)		2009/7/2
	應用說明	TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)		2007/9/4
	應用說明	Thermal Considerations for the DM64xx, DM64x, and C6000 Devices		2007/5/20
	使用指南	TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E)		2007/4/11
	使用指南	TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G)		2006/12/14
	使用指南	TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide (Rev. A)		2006/11/7
	使用指南	TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C)		2006/1/1
	使用指南	TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C)		2005/3/1
	使用指南	TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B)		2005/1/25
	使用指南	TMS320C620x/C670x DSP Program & Data Memory Controller/DMA Controller Ref.Guide (Rev. A)		2004/9/3
	使用指南	TMS320C6000 Chip Support Library API Reference Guide (Rev. J)		2004/8/13
	應用說明	TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)		2004/4/26
	應用說明	TMS320C6000 Board Design: Considerations for Debug (Rev. C)		2004/4/21
	應用說明	TMS320C6000 McBSP Initialization (Rev. C)		2004/3/8
	使用指南	TMS320C6000 DSP Interrupt Selector Reference Guide (Rev. A)		2004/1/9
	使用指南	TMS320C6000 DSP Designing for JTAG Emulation Reference Guide		2003/7/31
	使用指南	TMS320C620x/C670x DSP Boot Modes and Configuration Reference Guide		2003/7/31
	應用說明	How to Begin Development Today w/ High Performance Floating Point TMS320C67x DSP		2003/4/23
	應用說明	Using IBIS Models for Timing Analysis (Rev. A)		2003/4/15
	使用指南	TMS320C6201/6701 Evaluation Module User's Guide (Rev. F)		2002/8/13
	應用說明	TMS320C62x/C67x Power Consumption Summary (Rev. C)		2002/7/30
	應用說明	TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)		2002/6/4
	應用說明	TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C)		2002/4/17
	應用說明	TMS320C6000 DMA Example Applications (Rev. A)		2002/4/10
	應用說明	TMS320C6000 Board Design for JTAG (Rev. C)		2002/4/2
	應用說明	TMS320C6000 Memory Test (Rev. A)		2002/2/19
	應用說明	TMS320C6000 EMIF to External Flash Memory (Rev. A)		2002/2/13
	應用說明	Using a TMS320C6000 McBSP for Data Packing (Rev. A)		2001/10/31
	應用說明	Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A)		2001/9/30
	應用說明	TMS320C6000 Host Port to MC68360 Interface (Rev. A)		2001/9/30
	應用說明	Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)		2001/8/31
	應用說明	TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)		2001/8/31
	應用說明	TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)		2001/8/31
	應用說明	TMS320C6000 System Clock Circuit Example (Rev. A)		2001/8/15
	應用說明	TMS320C6201/6701 EVM: TMS320C6000 McBSP to Multimedia Audio Codec (Rev. A)		2001/7/24
	應用說明	TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)		2001/7/23
	應用說明	TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)		2001/7/10
	應用說明	TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)		2001/6/30
	應用說明	TMS320C6000 Host Port to MPC860 Interface (Rev. A)		2001/6/21
	應用說明	TMS320C6000 McBSP: IOM-2 Interface (Rev. A)		2001/5/21
	應用說明	Circular Buffering on TMS320C6000 (Rev. A)		2000/9/12
	應用說明	TMS320C6000 McBSP as a TDM Highway (Rev. A)		2000/9/11
	應用說明	TMS320C620x/TMS3206701 DMA and CPU: Data Access Performance (Rev. A)		2000/8/16
	應用說明	TMS320C6000 u-Law and a-Law Companding with Software or the McBSP		2000/2/2
	應用說明	TMS320C6000 C Compiler: C Implementation of Intrinsics		1999/12/7
	應用說明	TMS320C6000 McBSP: I2S Interface		1999/9/8

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The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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C64X-DSPLIB — Download TMS320C64x DSP Library

TMS320C6000 數位訊號處理器函式庫 (DSPLIB) 是適合 C 編程人員的平台最佳化 DSP 函式庫。此函式庫包括可呼叫 C 語言的通用訊號處理常式，通常用於運算密集的即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。DSPLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

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C67X-DSPLIB — Download TMS320C67x DSP Library

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C67X-MATHLIB — DSP Math Library for C67x Floating Point Devices

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)

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FAXLIB — FAX library (FAXLIB) for C66x, C64x+ and C55x processors

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SPRC090 — Download TMS320C6000 Chip Support Library

晶片支援函式庫 (CSL) 提供了應用程式編程介面 (API)，可用來設定與控制 DSP 晶片內建的周邊設備，以實現易用性、各種 C6000 裝置間的相容性以及硬體抽象。透過提供標準化和可移植性，可縮短開發時間。特性部分列出的函式專門針對下列裝置進行了最佳化：C6201、C6202、C6203、C6204、C6205、C6211、C6410、C6412、C6413、C6414、C6415 、C6416、C6418、C6701、C6711、C6712、C6713、DA610、DM640、DM641 和 DM642。