TMS320C6743

現行

低功耗 C674x 浮點 DSP- 375MHz

立即訂購

產品規格表

document-pdfAcrobat TMS320C6743 Fixed- and Floating-Point Digital Signal Processor datasheet (Rev. D) (英文) PDF | HTML

使用指南

document-pdfAcrobat
OMAP-L137 C6000 DSP+ARM Processor Technical Reference Manual (Rev. D) (英文)
document-pdfAcrobat
TMS320C6743 DSP Technical Reference Manual (Rev. D) (英文)

TMS320C6743

現行

產品規格表

立即訂購

產品詳細資料

CPU

32-/64-bit

Frequency (MHz)

200, 375

Features

1 RTC, 3 enhanced-capture peripherals

Operating system

TI RTOS

Rating

Catalog

Operating temperature range (°C)

-40 to 125

CPU

32-/64-bit

Frequency (MHz)

200, 375

Features

1 RTC, 3 enhanced-capture peripherals

Operating system

TI RTOS

Rating

Catalog

Operating temperature range (°C)

-40 to 125

PBGA (ZKB)

256

289 mm² (17 mm × 17 mm)

HLQFP (PTP)

176

676 mm² (26 mm × 26 mm)

Applications
- Networking
- High-Speed Encoding
- Professional Audio™
Software Support
- TI DSP/BIOS™
- Chip Support Library and DSP Library
375-MHz TMS320C674x Fixed- and Floating-Point VLIW DSP Core
- Load-Store Architecture with Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  - Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units
  - Mixed-Precision IEEE Floating Point Multiply Supported up to:
    - 2 SP x SP -> SP Per Clock
    - 2 SP x SP -> DP Every Two Clocks
    - 2 SP x DP -> DP Every Three Clocks
    - 2 DP x DP -> DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop
  Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- 3000 MIPS and 2250 MFLOPS C674x
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 128KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
3.3-V LVCMOS I/Os
Two External Memory Interfaces:
- EMIFA
  - NOR (8-Bit-Wide Data)
  - NAND (8-Bit-Wide Data)
- EMIFB
  - 16-bit SDRAM, up to 128MB
Two Configurable 16550-Type UART Modules:
- UART0 with Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
One Serial Peripheral Interface (SPI) with One Chip Select
Multimedia Card (MMC)/Secure Digital (SD)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Real-Time Unit (PRU) Cores
  - 32-Bit Load-Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled Through Software to Save Power
  - Register 30 of each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
Two Multichannel Audio Serial Ports (McASPs):
- Supports TDM, I2S, and Similar Formats
- FIFO Buffers for Transmit and Receive
10/100 Mbps RMII Ethernet Media Access Controller (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Event Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch
Commercial or Automotive Temperature

Applications
- Networking
- High-Speed Encoding
- Professional Audio™
Software Support
- TI DSP/BIOS™
- Chip Support Library and DSP Library
375-MHz TMS320C674x Fixed- and Floating-Point VLIW DSP Core
- Load-Store Architecture with Nonaligned Support
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32- and 40-Bit) Functional Units
  - Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
  - Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
  - Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
- Two Multiply Functional Units
  - Mixed-Precision IEEE Floating Point Multiply Supported up to:
    - 2 SP x SP -> SP Per Clock
    - 2 SP x SP -> DP Every Two Clocks
    - 2 SP x DP -> DP Every Three Clocks
    - 2 DP x DP -> DP Every Four Clocks
  - Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Hardware Support for Modulo Loop
  Operation
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
C674x Instruction Set Features
- Superset of the C67x+ and C64x+ ISAs
- 3000 MIPS and 2250 MFLOPS C674x
- Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
C674x Two-Level Cache Memory Architecture
- 32KB of L1P Program RAM/Cache
- 32KB of L1D Data RAM/Cache
- 128KB of L2 Unified Mapped RAM/Cache
- Flexible RAM/Cache Partition (L1 and L2)
Enhanced Direct Memory Access Controller 3 (EDMA3):
- 2 Transfer Controllers
- 32 Independent DMA Channels
- 8 Quick DMA Channels
- Programmable Transfer Burst Size
3.3-V LVCMOS I/Os
Two External Memory Interfaces:
- EMIFA
  - NOR (8-Bit-Wide Data)
  - NAND (8-Bit-Wide Data)
- EMIFB
  - 16-bit SDRAM, up to 128MB
Two Configurable 16550-Type UART Modules:
- UART0 with Modem Control Signals
- 16-Byte FIFO
- 16x or 13x Oversampling Option
One Serial Peripheral Interface (SPI) with One Chip Select
Multimedia Card (MMC)/Secure Digital (SD)
Two Master and Slave Inter-Integrated Circuit (I²C Bus™)
Programmable Real-Time Unit Subsystem (PRUSS)
- Two Independent Programmable Real-Time Unit (PRU) Cores
  - 32-Bit Load-Store RISC Architecture
  - 4KB of Instruction RAM per Core
  - 512 Bytes of Data RAM per Core
  - PRUSS can be Disabled Through Software to Save Power
  - Register 30 of each PRU is Exported from the Subsystem in Addition to the Normal R31 Output of the PRU Cores
- Standard Power-Management Mechanism
  - Clock Gating
  - Entire Subsystem Under a Single PSC Clock Gating Domain
- Dedicated Interrupt Controller
- Dedicated Switched Central Resource
Two Multichannel Audio Serial Ports (McASPs):
- Supports TDM, I2S, and Similar Formats
- FIFO Buffers for Transmit and Receive
10/100 Mbps RMII Ethernet Media Access Controller (EMAC):
- IEEE 802.3 Compliant (3.3-V I/O Only)
- RMII Media-Independent Interface
- Management Data I/O (MDIO) Module
One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit Timers)
Three Enhanced Pulse Width Modulators (eHRPWMs):
- Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
- 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
- Dead-Band Generation
- PWM Chopping by High-Frequency Carrier
- Trip Zone Input
Three 32-Bit Event Capture (eCAP) Modules:
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
- Single-Shot Capture of up to Four Event Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch
Commercial or Automotive Temperature

The C6743 device is a low-power digital signal processor based on C674x DSP core. The device consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The C6743 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance.

The C6743 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 128-KB of memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I²C Bus interfaces; two multichannel audio serial ports (McASPs) with 14/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; two UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces (EMIFs): an asynchronous external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6743 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The C6743 device is a low-power digital signal processor based on C674x DSP core. The device consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The C6743 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance.

filter

尋找其它音訊與雷達 DSP SoC

下載觀看有字幕稿的影片影片

TI 提供有限的設計支援

使用此產品的現有專案具備有限的 TI 設計支援。若有提供，您可在此頁面找到相關資訊、工具和軟體。使用此產品的現有設計具備有限的 TI 設計支援。在 TI E2E™ 支援論壇中申請有限的設計支援。

技術文件

找不到結果。請清除您的搜尋條件，然後再試一次。

檢視所有 29

重要文件	類型	標題	格式選項	日期
*	資料表	TMS320C6743 Fixed- and Floating-Point Digital Signal Processor datasheet (Rev. D)	PDF \| HTML	2014/6/17
*	使用指南	OMAP-L137 C6000 DSP+ARM Processor Technical Reference Manual (Rev. D)		2016/9/21
*	使用指南	TMS320C6743 DSP Technical Reference Manual (Rev. D)		2016/9/21
*	勘誤表	TMS320C6743 Fixed/Floating-Point DSP SE (Silicon Revs 3.0, 2.1, 2.0, 1.1, & 1.0) (Rev. G)		2014/6/17
	應用說明	How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)	PDF \| HTML	2021/5/19
	使用指南	SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)		2020/6/1
	應用說明	Using DSPLIB FFT Implementation for Real Input and Without Data Scaling	PDF \| HTML	2019/6/11
	應用說明	Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx	PDF \| HTML	2019/4/25
	應用說明	TMS320C6747/45/43 Power Consumption Summary		2019/4/23
	應用說明	General Hardware Design/BGA PCB Design/BGA	PDF \| HTML	2019/2/22
	應用說明	McASP Design Guide - Tips, Tricks, and Practical Examples		2019/1/10
	應用說明	Plastic Ball Grid Array [PBGA] Application Note (Rev. B)		2015/8/13
	使用指南	System Analyzer User's Guide (Rev. F)		2013/11/18
	使用指南	TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U)		2012/8/21
	使用指南	TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W)		2012/8/21
	應用說明	Using the TMS320C6747/45/43 Bootloader (Rev. C)		2012/6/1
	應用說明	Using the OMAP-L1x7 Bootloader (Rev. G)		2012/6/1
	應用說明	Introduction to TMS320C6000 DSP Optimization		2011/10/6
	使用指南	TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (Rev. F)		2011/9/14
	白皮書	Software and Hardware Design Challenges Due to Dynamic Raw NAND Market		2011/5/19
	使用指南	TMS320C674x DSP Megamodule Reference Guide (Rev. A)		2010/8/3
	使用指南	TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B)		2010/7/30
	應用說明	OMAP-L137 TMS320C6747/6745/6743 Pin Multiplexing Utility (Rev. A)		2009/9/26
	應用說明	TMS320C6747/45/43 Complementary Products		2009/9/23
	白皮書	Efficient Fixed- and Floating-Point Code Execution on the TMS320C674x Core		2009/6/24
	應用說明	TMS320C6747/45/43 & OMAP-L1x7 USB Downstream Host Compliance Testing		2009/3/12
	應用說明	TMS320C6747/45/43 & OMAP-L1x7 USB Upstream Device Compliance Testing		2009/3/12
	應用說明	TMS320C674x/OMAP-L1x USB Compliance Checklist		2009/3/12
	使用指南	TMS320C674x DSP Cache User's Guide (Rev. A)		2009/2/11

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

TMDSOSKL137 — OMAP-L137/TMS320C6747 浮點入門套件

與 Spectrum Digital Inc. 聯合開發的 OMAP-L137/TMS320C6747 浮點入門套件是低成本開發平台，設計目的在於加快基於 TI OMAP-L13x 應用處理器和 TMS320C674x 定點/浮點 DSP (TMS320C6747、TMS320C6745 和 TMS320C6743) 的高精密度應用開發速度。該套件使用 USB 通訊來真正發揮即插即用功能。資深和新進設計人員都可以使用該入門套件的全方位 Code Composer Studio™ 整合開發環境 (IDE) 和 eXpressDSP™ 軟體 (包含 DSP/BIOS™ 核心) (...)

支援產品和硬體

有庫存

限制：

登入以進行訂購

lock

登入以檢視庫存

??asset.out-of-stock-ti_zh_TW??

無法提供

偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器（模擬器）。對於大多數裝置，建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。

XDS200 透過 TI 20 接腳連接器（配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器）連接到目標電路板，並透過 USB2.0 高速 (...)

支援產品和硬體

有庫存

限制：

登入以進行訂購

lock

登入以檢視庫存

??asset.out-of-stock-ti_zh_TW??

無法提供

偵錯探測器

TMDSEMU560V2STM-U — XDS560™ 軟體 v2 系統追蹤 USB 偵錯探測器

XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。請注意，其不支援序列線偵錯 (SWD)。

所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)

支援產品和硬體

有庫存

限制：

登入以進行訂購

lock

登入以檢視庫存

??asset.out-of-stock-ti_zh_TW??

無法提供

偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

支援產品和硬體

有庫存

限制：

登入以進行訂購

lock

登入以檢視庫存

??asset.out-of-stock-ti_zh_TW??

無法提供

偵錯探測器

LB-3P-TRACE32-DSP — 適用於數位訊號處理器 (DSP) 的 Lauterbach TRACE32 偵錯和追蹤系統

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

從：Lauterbach GmbH

支援產品和硬體

檢視選項

軟體開發套件 (SDK)

PROCESSOR-SDK-C6747 — 適用於 C6747 處理器的處理器 SDK - 支援 TI-RTOS

處理器 SDK (軟體開發套件) 是一套專為 TI 嵌入式處理器所設計的整合軟體平台，提供簡易設定，可迅速且立即執行基準測試與示範。所有 TI 代表產品的處理器 SDK 版本均相同，開發人員能順暢地在其他裝置上再次使用軟體，與移轉軟體至其他裝置。有了處理器 SDK 和 TI 嵌入式處理器解決方案，讓開發可調式平台解決方案從此變得更輕鬆簡單。

C6747、C6745 和 C6743 的處理器 SDK 包含對 TI-RTOS 作業系統的支持。

RTOS 主要特點：

TI RTOS 核心，這是一套適用於 TI 裝置的輕量即時嵌入式作業系統
晶片支援函式庫、驅動程式和基礎電路板支援公用程式
最佳化 (...)

支援產品和硬體

檢視選項

IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

支援產品和硬體

啟動

下載選項

驅動程式或資料庫

AEC-AER — Acoustic echo cancellation/removal for TI C64x+, C674x, C55x and Cortex®-A8 processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支援產品和硬體

下載選項

驅動程式或資料庫

C64X-DSPLIB — Download TMS320C64x DSP Library

TMS320C6000 數位訊號處理器函式庫 (DSPLIB) 是適合 C 編程人員的平台最佳化 DSP 函式庫。此函式庫包括可呼叫 C 語言的通用訊號處理常式，通常用於運算密集的即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。DSPLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

支援產品和硬體

下載選項

驅動程式或資料庫

C67X-DSPLIB — Download TMS320C67x DSP Library

查看基準測試：DSP 核心基準測試

支援產品和硬體

下載選項

驅動程式或資料庫

C67X-MATHLIB — DSP Math Library for C67x Floating Point Devices

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)

支援產品和硬體

下載選項

驅動程式或資料庫

FAXLIB — FAX library (FAXLIB) for C66x, C64x+ and C55x processors

支援產品和硬體

下載選項

驅動程式或資料庫

SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)

C5000 6000 影像處理庫 (IMGLIB) 是適合 C 程式設計工具的最佳化影像/影片處理函式庫。此函式庫包括 C 可呼叫通用影像/影片處理常式，這些常式通常用於運算密集型即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。IMGLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。

查看基準測試：DSP 核心基準測試

支援產品和硬體

檢視選項

驅動程式或資料庫

VOLIB — Voice library (VoLIB) for C66x, C64x+ and C55x processors

支援產品和硬體

下載選項

軟體轉碼器

ADT-3P-DSPVOIPCODECS — 適應性數位技術 DSP VOIP、語音和音訊轉碼器

Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide (...)

從：Adaptive Digital Technologies, Inc.

支援產品和硬體

檢視選項

模擬型號