TMS320DM8148
- High-Performance
DaVinci Video Processors
- Up to 1-GHz ARM® Cortex®-A8 RISC Core
- Up to 750-MHz C674x™ VLIW DSP
- Up to 6000 MIPS and 4500 MFLOPS
- Fully Software-Compatible with C67x+™, C64x+™
- ARM Cortex-A8
Core
- ARMv7 Architecture
- In-Order, Dual-Issue, Superscalar Processor Core
- Neon™ Multimedia Architecture
- Supports Integer and Floating Point
- Jazelle® RCT Execution Environment
- ARMv7 Architecture
- ARM Cortex-A8 Memory Architecture
- 32KB of Instruction and Data Caches
- 512KB of L2 Cache
- 64KB of RAM, 48KB of Boot ROM
- TMS320C674x
Floating-Point VLIW DSP
- 64 General-Purpose Registers (32-Bit)
- Six ALU (32-/40-Bit) Functional Units
- Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
- Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks
- Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle
- Two Multiply
Functional Units
- Mixed-Precision IEEE Floating-Point Multiply Supported up
to:
- 2 SP x SP → SP Per Clock
- 2 SP x SP → DP Every Two Clocks
- 2 SP x DP → DP Every Three Clocks
- 2 DP x DP → DP Every Four Clocks
- Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle
- Mixed-Precision IEEE Floating-Point Multiply Supported up
to:
- C674x
Two-Level Memory Architecture
- 32KB of L1P RAM/Cache With EDC
- 32KB of L1D RAM/Cache
- 256KB of L2 Unified Mapped RAM/Caches With ECC
- System Memory Management Unit
(MMU)
- Maps C674x DSP and EDMA TC Memory Accesses to System Addresses
- 128KB of On-Chip Memory Controller (OCMC) RAM
- Imaging Subsystem (ISS)
- Camera Sensor
Connection
- Parallel Connection for Raw (up to 16-Bit) and BT.656 or BT.1120 (8- and 16-Bit)
- Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor
- Resizer
- Resizing Image and Video From 1/16x to 8x
- Generating Two Different Resizing Outputs Concurrently
- Camera Sensor
Connection
- Programmable
High-Definition Video Image Coprocessing (HDVICP v2) Engine
- Encode, Decode, Transcode Operations
- H.264, MPEG-2, VC-1, MPEG-4, SP/ASP, JPEG/MJPEG
- Media Controller
- Controls the HDVPSS, HDVICP2, and ISS
- SGX530 3D Graphics Engine
- Delivers up to 25 MPoly/sec
- Universal Scalable Shader Engine
- Direct3D Mobile, OpenGLES 1.1 and 2.0, OpenVG 1.0, OpenMax API Support
- Advanced Geometry DMA Driven Operation
- Programmable HQ Image Anti-Aliasing
- Endianness
- ARM and DSP Instructions/Data – Little Endian
- HD Video
Processing Subsystem (HDVPSS)
- Two 165-MHz, 2-channel HD
Video Capture Modules
- One 16-/24-Bit Input or Dual 8-Bit SD Input Channels
- One 8-/16-/24-Bit Input and One 8-Bit Only Input Channels
- Two 165-MHz HD Video
Display Outputs
- One 16-, 24-, or 30-Bit Output and One 16- or 24-Bit Output
- Composite or S-Video Analog Output
- Macrovision® Support Available
- Digital HDMI 1.3 Transmitter With Integrated PHY
- Advanced Video Processing Features Such as Scan, Format, Rate Conversion
- Three Graphics Layers and Compositors
- Two 165-MHz, 2-channel HD
Video Capture Modules
- Dual 32-Bit
DDR2/DDR3 SDRAM Interfaces
- Supports up to DDR2-800 and DDR3-1066
- Up to Eight x 8 Devices Total 2GB of Total Address Space
- Dynamic Memory Manager (DMM)
- Programmable Multi-Zone Memory Mapping and Interleaving
- Enables Efficient 2D Block Accesses
- Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
- Optimizes Interlaced Accesses
- General-Purpose Memory Controller
(GPMC)
- 8- or 16-Bit Multiplexed Address and Data Bus
- 512MB of Address Space Divided Among up to 8 Chip Selects
- Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM
- Error Locator Module (ELM) Outside of GPMC to Provide Up to 16-Bit or 512-Byte Hardware ECC for NAND
- Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and so Forth
- Enhanced Direct Memory Access (EDMA)
Controller
- Four Transfer Controllers
- 64 Independent DMA Channels and 8 Independent QDMA Channels
- Dual Port Ethernet
(10/100/1000 Mbps) With Optional Switch
- IEEE 802.3 Compliant (3.3-V I/O Only)
- MII/RMII/GMII/RGMII Media Independent Interfaces
- Management Data I/O (MDIO) Module
- Reset Isolation
- IEEE 1588 Time-Stamping and Industrial Ethernet Protocols
- Dual USB 2.0 Ports With
Integrated PHYs
- USB2.0 High- and Full-Speed Clients
- USB2.0 High-, Full-, and Low-Speed Hosts, or OTG
- Supports End Points 0–15
- One
PCI Express 2.0 Port With Integrated PHY
- Single Port With One Lane at 5.0 GT/s
- Configurable as Root Complex or Endpoint
- Eight 32-Bit General-Purpose Timers (Timer1–8)
- One System Watchdog Timer (WDT0)
- Six Configurable
UART/IrDA/CIR Modules
- UART0 With Modem Control Signals
- Supports up to 3.6864 Mbps UART0/1/2
- Supports up to 12 Mbps UART3/4/5
- SIR, MIR, FIR (4.0 MBAUD), and CIR
- Four Serial Peripheral
Interfaces (SPIs) (up to
48 MHz)- Each With Four Chip Selects
- Three MMC/SD/SDIO Serial
Interfaces (up to
48 MHz)- Three Supporting up to 1-, 4-, or 8-Bit Modes
- Dual Controller Area Network
(DCAN) Modules
- CAN Version 2 Part A, B
- Four Inter-Integrated Circuit (I2C Bus) Ports
- Six Multichannel Audio
Serial Ports (McASPs)
- Dual Ten Serializer Transmit and Receive Ports
- Quad Four Serializer Transmit and Receive Ports
- DIT-Capable For S/PDIF (All Ports)
- Multichannel Buffered Serial Port
(McBSP)
- Transmit and Receive Clocks up to 48 MHz
- Two Clock Zones and Two Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- Serial ATA (SATA) 3.0 Gbps Controller With
Integrated PHY
- Direct Interface to One Hard Disk Drive
- Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
- Supports Port Multiplier and Command-Based Switching
- Real-Time Clock
(RTC)
- One-Time or Periodic Interrupt Generation
- Up to 128 General-Purpose I/O (GPIO) Pins
- One Spin Lock Module with up to 128 Hardware Semaphores
- One Mailbox Module with 12 Mailboxes
- On-Chip ARM ROM Bootloader (RBL)
- Power, Reset,
and Clock Management
- Multiple Independent Core Power Domains
- Multiple Independent Core Voltage Domains
- Support for Three Operating Points (OPP100, OPP120, OPP166) per Voltage Domain
- Clock Enable and Disable Control for Subsystems and Peripherals
- 32KB of Embedded Trace
Buffer (ETB) and
5-Pin Trace Interface for Debug - IEEE 1149.1 (JTAG) Compatible
- 684-Pin Pb-Free BGA Package (CYE Suffix), 0.8-mm Ball Pitch With Via Channel Technology to Reduce PCB Cost
- 45-nm CMOS Technology
- 1.8- and 3.3-V Dual Voltage Buffers for General I/O
TMS320DM814x DaVinci video processors are highly integrated, programmable platforms that leverage the DaVinci processor technology to meet the processing needs of the following applications to name a few: HD Video Conferencing - Skype endpoints Video Surveillance DVRs IP Netcam Digital Signage Media Players and Adapters Mobile Medical Imaging Network Projectors Home Audio and Video Equipment
The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set.
The TMS320DM814x DaVinci video processors also present OEMs and ODMs with new levels of processor scalability and software reuse. An OEM or ODM that used the AM387x processors in a design and can make a similar product with added features could scale up to the pin-compatible and software-compatible TMS320DM814x processors from TI. The TMS320DM814x DaVinci video processors add a powerful C674x DSP core along with a video encoder and decoder to the hardware on the AM38x. Additionally, OEMs or ODMs that have used the AM387x or DM814x processors and find a need for a faster ARM and DSP core performance could scale up to the software-compatible AM389x or TMS320DM816x devices with higher core speeds.
Programmability is provided by an ARM Cortex-A8 RISC CPU with Neon extension, TI C674x VLIW floating-point DSP core, and high-definition video and imaging coprocessors. The ARM lets developers keep control functions separate from A/V algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-Bit RISC Core with Neon floating-point extension includes: 32KB of Instruction cache; 32KB of Data cache; 512KB of L2 Cache; 48KB of Boot ROM; and 64KB of RAM.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem Dual Port Gigabit Ethernet MACs (10/100/1000 Mbps) [Ethernet Switch] with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping and Industrial Ethernet ProtocolsTwo USB ports with integrated 2.0 PHY PCIe x1 GEN2 Compliant interfaceTwo 10-serializer McASP audio serial ports (with DIT mode)Four quad-serilaizer McASP audio serial ports (with DIT mode)One McBSP multichannel buffered serial portSix UARTs with IrDA and CIR supportFour SPI serial interfacesThree MMC/SD/SDIO serial interfacesFour I2C master and slave interfaces Parallel Camera Interface (CAM)Up to 128 General-Purpose I/Os (GPIOs)Eight 32-bit general-purpose timers System watchdog timer Dual DDR2, and DDR3 SDRAM interfacesFlexible 8- or 16-bit asynchronous memory interfaceTwo Controller Area Network (DCAN) modulesSpin LockMailboxSerial Hard Disk Drive Interface (SATA 300)
The TMS320DM814x DaVinci video processors also include a high-definition video and imaging coprocessor 2 (HDVICP2), and an SGX530 3D graphics engine to off-load many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. Additionally, it has a complete set of development tools for both the ARM and DSP, which include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Microsoft® Windows® debugger interface for visibility into source code execution.
The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000 DSP platform and is code-compatible with previous generation C64x Fixed-Point and C67x Floating-Point DSP generation. The C674x Floating-Point DSP processor uses 32KB of L1 program memory with EDC and 32KB of L1 data memory. Up to 32KB of L1P can be configured as program cache. The remaining memory is noncacheable no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining memory is noncacheable no-wait-state data memory. The DSP has 256KB of L2 RAM with ECC, which can be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip memory accesses are routed through an MMU.
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Z3-3P-VIDEO-EVMS — Z3 技術處理器視訊評估模組
TMDSEMU200-U — XDS200 USB 偵錯探測器
XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器（模擬器）。對於大多數裝置，建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。
XDS200 透過 TI 20 接腳連接器（配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器）連接到目標電路板，並透過 USB2.0 高速 (...)
TMDSEMU560V2STM-U — XDS560™ 軟體 v2 系統追蹤 USB 偵錯探測器
XDS560v2 是 XDS560™ 系列偵錯探測器中性能最高的，且同時支援傳統 JTAG 標準 (IEEE1149.1) 與 cJTAG (IEEE1149.7)。 請注意，其不支援序列線偵錯 (SWD)。
所有 XDS 偵錯探測器均在所有配備嵌入式追蹤緩衝器 (ETB) 的 ARM 與 DSP 處理器中支援核心與系統追蹤。 對於針腳上的追蹤，則需要 XDS560v2 PRO TRACE。
XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (...)
TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器
The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).
All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)
LINUXEZSDK-DAVINCI — Linux EZ Software Development Kit (EZSDK) for DM814x and DM816x - ALPHA
Linux EZ 軟體開發套件 (EZ SDK) 可讓客戶在數分鐘內評估其裝置，並在一小時內開始開發。此套件可提供 DaVinci™ 開發人員評估及開始在 DaVinci™ DM816x/DM814x 處理器上進行開發所需的一切。隨附的圖形使用者介面 (GUI) 架構應用程式啟動器，可快速啟動示範，基準測試和應用程式。此外，開發人員還會發現開發應用程式並將其添加到應用程式啟動器變得十分容易。EZ SDK 也包括視訊/音訊編解碼器和 DSP 加速演算法，以及 C6EZRun 和 C6EZAccel 等工具，讓 ARM 開發人員能輕鬆運用 DSP 執行訊號處理任務。
DaVinci Linux (...)
SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)
C5000 6000 影像處理庫 (IMGLIB) 是適合 C 程式設計工具的最佳化影像/影片處理函式庫。此函式庫包括 C 可呼叫通用影像/影片處理常式，這些常式通常用於運算密集型即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。IMGLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。
查看基準測試：DSP 核心基準測試
SPRC265 — TMS320C6000 DSP 函式庫 (DSPLIB)
TMS320C6000 數位訊號處理器函式庫 (DSPLIB) 是適合 C 編程人員的平台最佳化 DSP 函式庫。此函式庫包括可呼叫 C 語言的通用訊號處理常式，通常用於運算密集的即時應用。相較於同等標準 ANSI C 語言程式碼，使用這些常式可以實現更高性能。DSPLIB 透過立即可用的 DSP 功能與原始程式碼，能夠大幅縮短應用程式開發時間。
查看基準測試：DSP 核心基準測試
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCBGA (CYE) | 684 | Ultra Librarian |
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