TPS752-Q1
- Qualified for Automotive Applications
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- 2-A Low-Dropout Voltage Regulator
- Available in 1.5-V, 1.8-V, 2.5-V, 3.3-V Fixed Output and Adjustable Versions
- Open Drain Power-On Reset With 100-ms Delay (TPS752xx)
- Open Drain Power-Good (PG) Status Output (TPS754xx)
- Dropout Voltage Typically 210 mV at 2 A (TPS75233)
- Ultralow 75-µA Typical Quiescent Current
- Fast Transient Response
- 2% Tolerance Over Specified Conditions for Fixed-Output Versions
- 20-Pin TSSOP (PWP) PowerPAD™ Package
- Thermal Shutdown Protection
PowerPAD is a trademark of Texas Instruments.
The TPS752xx and TPS754xx are low-dropout regulators with integrated power-on reset and power good (PG) functions, respectively. These devices are capable of supplying 2 A of output current with a dropout of 210 mV (TPS75233, TPS75433). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. TPS752xx and TPS754xx are designed to have fast transient response for larger load current changes.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 210 mV at an output current of 2 A for the TPS75x33) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 1 µA at TJ = 25°C.
The RESET (SVS, POR, or power on reset) output of the TPS752xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., over load condition) of its regulated voltage.
The TPS754xx has a power good terminal (PG) as an active high, open drain output, which can be used to implement a power-on reset or a low-battery indicator.
The TPS752xx or the TPS754xx are offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS752xx and the TPS754xx families are available in 20 pin TSSOP (PWP) packages.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Fast-Transient-Response 2-A Low-Dropout Voltage Regulators datasheet (Rev. C) | 2008年 4月 30日 | |
| Application note | LDO Noise Demystified (Rev. B) | PDF | HTML | 2020年 8月 18日 | |
| Application note | LDO PSRR Measurement Simplified (Rev. A) | PDF | HTML | 2017年 8月 9日 |
設計與開發
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| 封裝 | 引腳 | 下載 |
|---|---|---|
| HTSSOP (PWP) | 20 | 檢視選項 |
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