TPS7A33
- Input Voltage Range: –3 V to –36 V
- Noise:
- 16 µVRMS (10 Hz to 100 kHz)
- Power-Supply Ripple Rejection:
- 72 dB (10 kHz)
- Adjustable Output: –1.18 V to –33 V
- Maximum Output Current: 1 A
- Stable With Ceramic Capacitors ≥ 10 µF
- Built-In Current-Limit and Thermal Shutdown
Protection - Available in an External Heatsink-Capable, High
Thermal Performance TO-220 Package - Operating Temperature Range:
–40°C to 125°C
The TPS7A33 series of linear regulators are negative voltage (–36 V), ultralow-noise (16-µVRMS, 72-dB PSRR) linear regulators capable of sourcing a maximum load of 1 A.
The TPS7A33 series include a complementary metal oxide semiconductor (CMOS) logic-level-compatible enable pin (EN) to allow for user-customizable power management schemes. Other features available include built-in current limit and thermal shutdown features to protect the device and system during fault conditions.
The TPS7A33 family is designed using bipolar technology primarily for high-accuracy, high-precision instrumentation applications, where clean voltage rails are critical to maximize system performance. This feature makes it ideal to power operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other high-performance analog circuitry.
In addition, the TPS7A33 family of linear regulators is suitable for post DC-DC converter regulation. By filtering out the output voltage ripple inherent to DC-DC switching conversion, maximum system performance is ensured in sensitive instrumentation, medical, test and measurement, audio, and RF applications.
For applications where positive and negative high-performance rails are required, consider the TPS7A4700 positive high-voltage, ultralow-noise, low-dropout linear regulator as well.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | TPS7A33 –36-V, 1-A, Ultralow-Noise Negative Voltage Regulator datasheet (Rev. D) | PDF | HTML | 2013/10/18 | ||
| 白皮書 | Reduce System Noise Using Parallel LDOs | PDF | HTML | 2025/11/3 | |||
| 白皮書 | Parallel LDO Architecture Design Using Ballast Resistors | PDF | HTML | 2022/12/14 | |||
| 白皮書 | Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast | PDF | HTML | 2022/12/13 | |||
| 應用說明 | A Topical Index of TI LDO Application Notes (Rev. F) | 2019/6/27 | ||||
| 技術文章 | Design a pre-tracking regulator, part 2: for a negative LDO | PDF | HTML | 2019/4/26 | |||
| 選擇指南 | Low Dropout Regulators Quick Reference Guide (Rev. P) | 2018/3/21 |
設計與開發
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DDC2256AEVM — DDC2256A 256 通道電流輸入類比轉數位轉換器評估模組
DDC2256AEVM 評估模組 (EVM) 是 DDC2256A (256 通道、電流輸入、24 位元類比轉數位 (A/D) 轉換器) 的評估套件。EVM 套件由 DUT 電路板和擷取板組成，包含兩個 DDC2256A 裝置、一個用於裝置通訊/配置的 FPGA、用於臨時資料儲存的 36MB 記憶體，以及一個用於連接 PC 的 USB 介面。EVM 包含所有必要的控制訊號及板載功率產生，因而大幅降低對外部設備的需求。最後，評估系統還為 Microsoft® Windows® 提供了易於使用的軟體。
TPS7A4701EVM-094 — TPS7A4701 射頻低壓差 (LDO) 電壓穩壓器評估模組
PARALLEL-LDO-CALC — Parallel low-dropout (LDO) calculator
並聯低壓差 (LDO) 計算器是以 Microsoft® Excel® 為基礎的工具，可為使用鎮流器電阻器的並聯 LDO 穩壓器提供最壞情況分析。此工具可幫助使用者判斷所需的並聯 LDO 穩壓器最小數量，以及適合系統要求集的最佳鎮流器電阻。
在並聯應用中使用的常用 LDO 穩壓器的產品規格書資訊會預先填入計算機中。使用者可根據自己的系統需求，評估最符合其系統需求的 LDO 穩壓器裝置。
許多 TI 參考設計包含 TPS7A33
使用我們的參考設計選擇工具，以檢視並找出最適合您的應用和參數的設計。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGW) | 20 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。