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線性與低壓差 (LDO) 穩壓器

TPS7A52

現行

2-A、低 VIN (1.1-V)、低雜訊、高準確度、超低壓差 (LDO) 電壓穩壓器

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產品規格表

TPS7A52

現行
產品規格表 立即訂購

產品詳細資料

Rating Catalog Vin (max) (V) 6.5 Vin (min) (V) 1.1 Iout (max) (A) 2 Output options Adjustable Output Vout (max) (V) 5.15 Vout (min) (V) 0.8 Noise (µVrms) 4.4 PSRR at 100 KHz (dB) 45 Iq (typ) (mA) 2.8 Features Enable, Foldback Overcurrent protection, Output discharge, Power good, Soft start Thermal resistance θJA (°C/W) 46.5 Load capacitance (min) (µF) 22 Regulated outputs (#) 1 Accuracy (%) 0.5 Dropout voltage (Vdo) (typ) (mV) 40 Operating temperature range (°C) -40 to 125
Rating Catalog Vin (max) (V) 6.5 Vin (min) (V) 1.1 Iout (max) (A) 2 Output options Adjustable Output Vout (max) (V) 5.15 Vout (min) (V) 0.8 Noise (µVrms) 4.4 PSRR at 100 KHz (dB) 45 Iq (typ) (mA) 2.8 Features Enable, Foldback Overcurrent protection, Output discharge, Power good, Soft start Thermal resistance θJA (°C/W) 46.5 Load capacitance (min) (µF) 22 Regulated outputs (#) 1 Accuracy (%) 0.5 Dropout voltage (Vdo) (typ) (mV) 40 Operating temperature range (°C) -40 to 125
VQFN-HR (RPS) 12 5.5 mm² (2.5 mm × 2.2 mm)
  • 0.5% (max) accuracy over line, load, and temperature with BIAS
  • Output voltage noise: 4.4 µVRMS
  • Low dropout: 65 mV (max) at 2 A with BIAS
  • Output voltage noise: 4.4 µVRMS
  • Power-supply ripple rejection:
    • 40 dB at 500 kHz
  • Input voltage range:
    • Without BIAS: 1.4 V to 6.5 V
    • With BIAS: 1.1 V to 6.5 V
  • Adjustable output voltage range: 0.8 V to 5.2 V
  • Adjustable soft-start inrush control
  • Open-drain, power-good (PG) output
  • 2.2-mm × 2.5-mm, 12-pin VQFN package
  • 0.5% (max) accuracy over line, load, and temperature with BIAS
  • Output voltage noise: 4.4 µVRMS
  • Low dropout: 65 mV (max) at 2 A with BIAS
  • Output voltage noise: 4.4 µVRMS
  • Power-supply ripple rejection:
    • 40 dB at 500 kHz
  • Input voltage range:
    • Without BIAS: 1.4 V to 6.5 V
    • With BIAS: 1.1 V to 6.5 V
  • Adjustable output voltage range: 0.8 V to 5.2 V
  • Adjustable soft-start inrush control
  • Open-drain, power-good (PG) output
  • 2.2-mm × 2.5-mm, 12-pin VQFN package

The TPS7A52 is a low-noise (4.4 µVRMS), ultra-low dropout linear regulator (LDO) capable of sourcing 2 A with only 65 mV of maximum dropout. The device output voltage is adjustable from 0.8 V to 5.2 V using an external resistor divider.

The combination of low noise (4.4 µVRMS), high PSRR, and high output current capability makes the TPS7A52 an excellent choice to power noise-sensitive components such as those found in high-speed communications, video, medical, or test-and-measurement applications. The high performance of this device limits power-supply-generated phase noise and clock jitter, making this device ideal for powering high-performance serializer and deserializer (SerDes), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Specifically, RF amplifiers benefit from the high performance and 5.2-V output capability of the device.

For digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs)] requiring low-input voltage, low-output (LILO) voltage operation, the exceptional accuracy (0.5% over load and temperature), remote sensing, excellent transient performance, and soft-start capabilities of the TPS7A52 provides optimal system performance.

As an adjustable voltage regulator, there is versatility in the design of the TPS7A52 that makes the device a component of choice for analog loads such as voltage-controlled oscillator (VCO), ADC, DAC, and imaging sensors and for digital loads such as SerDes, FPGAs, and DSPs.

 

The TPS7A52 is a low-noise (4.4 µVRMS), ultra-low dropout linear regulator (LDO) capable of sourcing 2 A with only 65 mV of maximum dropout. The device output voltage is adjustable from 0.8 V to 5.2 V using an external resistor divider.

The combination of low noise (4.4 µVRMS), high PSRR, and high output current capability makes the TPS7A52 an excellent choice to power noise-sensitive components such as those found in high-speed communications, video, medical, or test-and-measurement applications. The high performance of this device limits power-supply-generated phase noise and clock jitter, making this device ideal for powering high-performance serializer and deserializer (SerDes), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Specifically, RF amplifiers benefit from the high performance and 5.2-V output capability of the device.

For digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs)] requiring low-input voltage, low-output (LILO) voltage operation, the exceptional accuracy (0.5% over load and temperature), remote sensing, excellent transient performance, and soft-start capabilities of the TPS7A52 provides optimal system performance.

As an adjustable voltage regulator, there is versatility in the design of the TPS7A52 that makes the device a component of choice for analog loads such as voltage-controlled oscillator (VCO), ADC, DAC, and imaging sensors and for digital loads such as SerDes, FPGAs, and DSPs.

 
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 TPS7A52 2-A, High-Accuracy (0.5%), Low-Noise (4.4 µVRMS), LDO Voltage Regulator datasheet (Rev. A) PDF | HTML 2020/3/23
白皮書 Demystifying LDO Turn-On (Start-Up) Time (Rev. B) PDF | HTML 2026/3/10
白皮書 Reduce System Noise Using Parallel LDOs PDF | HTML 2025/11/3
白皮書 Parallel LDO Architecture Design Using Ballast Resistors PDF | HTML 2022/12/14
白皮書 Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast PDF | HTML 2022/12/13
應用說明 Point-of-Load Solutions for Network Interface Cards (NIC) PDF | HTML 2021/9/8
技術文章 Minimize noise and ripple with a low-noise buck converter PDF | HTML 2020/10/21

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開發板

TPS7A52EVM-031 — TPS7A52 2-A 低 VIN (1.1-V) 低雜訊高準確度超 LDO 電壓穩壓器評估模組

TPS7A52 評估模組 (EVM) 爲典型配置設計，用於評估 TPS7A52 裝置的運作和性能，TPS7A54 是一款高準確度、2-A、低 VIN、低-VOUT、低壓差 (LDO) 電壓穩壓器。

EVM 電路板主要配置爲參考設計，可供需要高達 2 A 動態負載電流的工程應用。

使用指南: PDF
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模擬型號

TPS7A5201RPS PSpice Model (Rev. A)

SBVM952A.ZIP (3263 KB) - PSpice 模型
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計算工具

PARALLEL-LDO-CALC — Parallel low-dropout (LDO) calculator

並聯低壓差 (LDO) 計算器是以 Microsoft® Excel® 為基礎的工具，可為使用鎮流器電阻器的並聯 LDO 穩壓器提供最壞情況分析。此工具可幫助使用者判斷所需的並聯 LDO 穩壓器最小數量，以及適合系統要求集的最佳鎮流器電阻。

在並聯應用中使用的常用 LDO 穩壓器的產品規格書資訊會預先填入計算機中。使用者可根據自己的系統需求，評估最符合其系統需求的 LDO 穩壓器裝置。

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參考設計

TIDA-060043 — 56G 重定時器 MCB QSFP-DD 參考設計

此參考設計展現 56G PAM-4 重定時器 DS560DF410 如何用於將主動式電力電纜應用中的高速訊號等化。此設計是模組相容電路板 (MCB)，可將來自 QSFP-DD 連接器的訊號透過重定時器，以入口和出口方向傳送至 SMA 和 MXP 連接器。

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VQFN-HR (RPS) 12 Ultra Librarian
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