TPS7A53B
- Accuracy over line, load, and temperature with BIAS: 0.5%
- Output voltage noise: 4.6µVRMS
- Low dropout: 110mV (max) at 3A with BIAS
- Power-supply rejection ratio:
- 48dB at 500kHz
- Input voltage range:
- Without BIAS: 1.4V to 6.5V
- With BIAS: 1.1V to 6.5V
- Adjustable output voltage range: 0.5V to 5.15V
- Adjustable soft-start inrush control
- Open-drain, power-good (PG) output
- 2.5mm × 2.2mm, 12-pin VQFN package
The TPS7A53B is a low-noise (4.6µVRMS), ultra-low dropout linear regulator (LDO) capable of sourcing 3A with only 110mV of maximum dropout. The device output voltage is adjustable from 0.5V to 5.15V using an external resistor divider.
The combination of low noise (4.6µVRMS), high PSRR, and high output current capability makes the TPS7A53B a great solution for powering noise-sensitive components. Applications include high-speed communications, video, medical, or test and measurement. The high PSRR and low noise performance of this device limits power-supply-generated phase noise and clock jitter, making this device a good choice for powering high-performance serializers and deserializers (SerDes), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Specifically, RF amplifiers benefit from the high performance and 5.15V output capability of the device.
For digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs)] requiring low-input, low-output (LILO) voltage operation, the exceptional accuracy (0.5% over load and temperature), remote sensing, excellent transient performance, and soft-start capabilities of the TPS7A53B provides optimal system performance.
As an adjustable voltage regulator, the design of the TPS7A53B offers versatility. This versatility makes the device a component of choice for analog loads such as voltage-controlled oscillators (VCOs), ADCs, DACs, and imaging sensors and for digital loads such as SerDes, FPGAs, and DSPs.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | TPS7A53B 3A, Low-Input Voltage, Low-Noise, High-Accuracy, Low-Dropout (LDO) Voltage Regulator datasheet (Rev. A) | PDF | HTML | 2024/1/19 | ||
| 白皮書 | Demystifying LDO Turn-On (Start-Up) Time (Rev. B) | PDF | HTML | 2026/3/10 | |||
| 白皮書 | Reduce System Noise Using Parallel LDOs | PDF | HTML | 2025/11/3 | |||
| 白皮書 | Parallel LDO Architecture Design Using Ballast Resistors | PDF | HTML | 2022/12/14 | |||
| 白皮書 | Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast | PDF | HTML | 2022/12/13 |
設計與開發
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TPS7A53EVM-031 — 適用於 3-A、低 VIN、低雜訊、高精確度超 LDO 電壓穩壓器的 TPS7A53 評估模組
TPS7A53 評估模組 (EVM) 爲典型配置設計，用於評估 TPS7A53 裝置的運作和性能，TPS7A54 是一款高準確度、3-A、低 VIN、低-VOUT、低壓差 (LDO) 電壓穩壓器。
EVM 電路板主要配置爲參考設計，可供需要高達 3 A 動態負載電流的工程應用。
PARALLEL-LDO-CALC — Parallel low-dropout (LDO) calculator
並聯低壓差 (LDO) 計算器是以 Microsoft® Excel® 為基礎的工具，可為使用鎮流器電阻器的並聯 LDO 穩壓器提供最壞情況分析。此工具可幫助使用者判斷所需的並聯 LDO 穩壓器最小數量，以及適合系統要求集的最佳鎮流器電阻。
在並聯應用中使用的常用 LDO 穩壓器的產品規格書資訊會預先填入計算機中。使用者可根據自己的系統需求，評估最符合其系統需求的 LDO 穩壓器裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN-HR (RPS) | 12 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。