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Global positioning system receiver

Products and reference designs
Block diagram

Global positioning system receiver

Block diagram

Overview

Our integrated circuits and reference designs help you develop high accuracy and jamming-resistant global positioning system (GPS) receivers.

Design requirements

Modern GPS receivers require:

  • Low noise analog front ends to enable reception of weak signals.
  • Low jitter LOs and clocks to maximize the performance of the digitizer.
  • Low noise power and efficient power solutions.
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Block diagram

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Technical documentation

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Type Title Date
User guide Understanding JESD204B Subclasses and Deterministic Latency 26 Oct 2012
Technical article Sequencing and powering FPGAs in radar and other defense applications PDF | HTML 26 Jun 2023
Analog Design Journal Designing a modern power supply for RF sampling converters 25 May 2017
Application note Common Design Challenges and Proper Use of Fully Differential Amplifiers (FDA) 25 May 2016
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) 21 Apr 2015
Analog Design Journal Designing for low distortion with high-speed op amps 16 Mar 2005
Technical article FPGA power made simple: system architecture PDF | HTML 15 Sep 2023
Application note LMX2571 Using a Programmable Input Multiplier to Minimize Integer Boundary Spurs 15 Feb 2017
Application note Frequency Margining Using TI High-Performance Clock Generators (Rev. A) 12 Dec 2015
Application note Keystone Error Detection and Correction EDC ECC (Rev. A) 10 May 2022
White paper The Impact of Various PLL Parameters on System Perf 10 Dec 2011
White paper Multicore SoCs stay a step ahead of SoC FPGAs 08 Mar 2016
Technical article Minimize noise and ripple with a low-noise buck converter PDF | HTML 07 Aug 2023
Technical article How to complete your RF sampling solution PDF | HTML 02 Aug 2023

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