ADS54J64EVM

ADS54J64 Quad-Channel, 14-Bit, 1-GSPS, 2x-Oversampling ADC Evaluation Module

ADS54J64EVM

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Overview

The ADS54J64 evaluation module (EVM) is used to evaluate the ADS54J64 quad-channel, 14-bit, 1-GSPS, 2x-oversampling analog-to-digital converter (ADC). The EVM has transformer-coupled analog inputs to accommodate a wide range of signal sources and frequencies. The EVM is designed to connect directly to a variety of data capture tools from TI including the TSW14J56EVM and TSW14J50EVM. Additional support is provided through the ADS58J64EVM GUI and the high-speed data converter pro software (DATACONVERTERPRO-SW) analysis tool. Also available is the ADS54J64EVM design package that includes schematics, Gerbers, and a bill of material (BOM).

The ADS54J64EVM features an FMC connector that also is compatible with many development kits from leading FPGA manufacturers.

Features
  • Transformer-coupled input network provides single-ended to differential signal conversion
  • LMK04828 (ultra-low jitter and phase noise clock) generates a complete JESD204B subclass 1 clocking solution simplifying the FPGA interface
  • Device registers programmed through a USB connector and FTDI USB-to-SPI bus translator when using the device software GUI
  • Standard FMC connector used for direct interface to TI TSW14J5xEVM data capture solutions and FPGA-based platforms
  • High-speed data converter pro software (DATACONVERTERPRO-SW) analysis tool provides complete environment for signal analysis including data capture and storage of ADC EVM output

  • ADS54J64 evaluation module
  • Mini-USB cable (2m)

 

High-speed ADCs (>10MSPS)
ADS54J64 Quad-Channel, 14-Bit, 1-GSPS, 2x-Oversampling Analog-to-Digital Converter (ADC)

 

Clock jitter cleaners & synchronizers
LMK04828 Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

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HARDWARE AND SOFTWARE PACKAGE

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Evaluation board

ADS54J64EVM – ADS54J64 Quad-Channel, 14-Bit, 1-GSPS, 2x-Oversampling ADC Evaluation Module

TI's Standard Terms and Conditions for Evaluation Items apply.

Design files

ADS54J64EVM Design Package (Rev. A) SBAC176A.ZIP (6424 KB)

Technical documentation

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Type Title Date
* User guide ADS54J64 Evaluation Module User's Guide Sep. 15, 2017
Certificate ADS54J64EVM EU Declaration of Conformity (DoC) Jan. 02, 2019
Data sheet ADS54J64 Quad-Channel, 14-Bit, 1-GSPS, 2x Oversampling, Analog-to-Digital Converter datasheet Oct. 09, 2017

Related design resources

Hardware development

EVALUATION BOARD
TSW14J50EVM Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-6.5Gbps TSW14J56EVM Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-12.5Gbps

Software development

SUPPORT SOFTWARE
DATACONVERTERPRO-SW High-speed data converter pro software

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