ADS58J64EVM

ADS58J64 Evaluation Module

ADS58J64EVM

Order now

Overview

The ADS58J64EVM is an evaluation board used to evaluate the ADS58J64 Integrated Receiver from Texas Instruments. The ADS58J64 is a low power, 14-bit, 500-MSPS, quad channel telecom receiver with a buffered analog input. The device supports JESD204B interface and data rates up to 10Gbps. The EVM has transformer coupled analog and clock inputs to support single ended signal and clock sources and also to accommodate a wide range of signal frequencies. The transformers at the analog input are connected back to back for better amplitude and phase matching performance. The on-board clock synthesizer/distribution chip, LMK04828 may be used to provide an ultra-low-jitter and phase noise device clock and matched system reference clocks(SYSREF) for the JESD204B interface of the ADC and data capture board (TSW14J56EVM). The ADS58J64 and LMK04828 are both controlled through an easy to use software Graphic User Interface (GUI).

The ADS58J64EVM can connect directly to the TSW14J56EVM via an FMC connector for data capture and subsequent analyses with the HSDCPRO software. The ADS58J64EVM can also be connected to any FPGA/ASIC evaluation module that includes an FMC connector.

Features
  • Transformer-coupled signal input network, allows a single-ended signal source to the EVM
  • On board system clock generator (LMK04828) generates the FPGA reference clock, ADC sampling clock and SYSREFs for the high-speed JESD204B serial interface
  • Default transformer-coupled clock input network enables testing the receiver performance with a very low-noise single ended clock source
  • Device register programming through a USB connector and easy to use software GUI
  • Compatible with TSW14J56 data capture board and HSDCPRO data analyses software

  • EVM circuit board
  • Power cable
  • USB cable

Receivers
ADS58J64 Quad-channel 14-bit 1-GSPS telecom receiver and feedback IC

 

Buck converters (integrated switch)
TPS54319 2.95 V to 6 V input, 3 A, 2 MHz SWIFT™ synchronous step-down converter in a 3 mm x 3 mm QFN package TPS62085 3-A Step-Down Converter with DCS-Control and Hiccup Short Circuit Protection in 2x2 HotRod Package

 

Clock jitter cleaners & synchronizers
LMK04828 Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

 

Linear regulators (LDO)
TPS74201 1.5-A, low-VIN (0.8-V), low-noise, high-PSRR, adjustable ultra-low-dropout voltage regulator TPS7A8101 1-A, high-PSRR, adjustable ultra-low-dropout voltage regulator with enable

 

eFuses & hot swap controllers
TPS2400 5.5-V over voltage protection controller with 100-V input transient protection
Download

Order & start development

Evaluation board

ADS58J64EVM – ADS58J64 Evaluation Module

Evaluation board

ADS58J64EVM-BDL – ADS58J64EVM + TSW14J57EVM Data Capture / Pattern Generator Bundle

GUI for evaluation module (EVM)

ADS58J64EVM GUI – SBAC161.ZIP (286345KB)

TI's Standard Terms and Conditions for Evaluation Items apply.

Design files

ADS58J64EVM Design Package SBAC162.ZIP (8451 KB)

Technical documentation

star
= Top documentation selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* User guide ADS58J64EVM User's Guide Jan. 09, 2017
More literature ADS58J64EVM EU Declaration of Conformity (DoC) Jan. 02, 2019

Related design resources

Hardware development

EVALUATION BOARD
TSW14J50EVM Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-6.5Gbps TSW14J56EVM Data capture/pattern generator: data converter EVM with 8 JESD204B lanes from 0.6-12.5Gbps TSW14J57EVM Data capture/pattern generator: data converter EVM with 16 JESD204B lanes from 1.6-15Gbps

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​

Videos