ADS58J64 Evaluation Module
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- ADS58J64EVM User's Guide
(PDF 4911 KB)
09 Jan 2017
The ADS58J64EVM is an evaluation board used to evaluate the ADS58J64 Integrated Receiver from Texas Instruments. The ADS58J64 is a low power, 14-bit, 500-MSPS, quad channel telecom receiver with a buffered analog input. The device supports JESD204B interface and data rates up to 10Gbps. The EVM has transformer coupled analog and clock inputs to support single ended signal and clock sources and also to accommodate a wide range of signal frequencies. The transformers at the analog input are connected back to back for better amplitude and phase matching performance. The on-board clock synthesizer/distribution chip, LMK04828 may be used to provide an ultra-low-jitter and phase noise device clock and matched system reference clocks(SYSREF) for the JESD204B interface of the ADC and data capture board (TSW14J56EVM). The ADS58J64 and LMK04828 are both controlled through an easy to use software Graphic User Interface (GUI).
The ADS58J64EVM can connect directly to the TSW14J56EVM via an FMC connector for data capture and subsequent analyses with the HSDCPRO software. The ADS58J64EVM can also be connected to any FPGA/ASIC evaluation module that includes an FMC connector.
- Transformer-coupled signal input network, allows a single-ended signal source to the EVM
- On board system clock generator (LMK04828) generates the FPGA reference clock, ADC sampling clock and SYSREFs for the high-speed JESD204B serial interface
- Default transformer-coupled clock input network enables testing the receiver performance with a very low-noise single ended clock source
- Device register programming through a USB connector and easy to use software GUI
- Compatible with TSW14J56 data capture board and HSDCPRO data analyses software