ADS54J64

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Quad-Channel, 14-Bit, 1-GSPS, 2x-Oversampling Analog-to-Digital Converter (ADC)

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Product details

Parameters

Sample rate (Max) (MSPS) 1000, 500 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 1000 Features High Performance Rating Catalog Input range (Vp-p) 1.1 Power consumption (Typ) (mW) 2500 Architecture Pipeline SNR (dB) 69 ENOB (Bits) 11.6 SFDR (dB) 86 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFNP (RMP) 72 100 mm² 10 x 10 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • Quad Channel, 14-Bit Resolution
  • Maximum Sampling Rate: 1 GSPS
  • Maximum Output Sample Rate: 500 MSPS
  • High-Impedance Analog Input Buffer
  • Analog Input Bandwidth (–3 dB): 1 GHz
  • Output Options:
    • Digital Down Conversion (DDC) Using 16-Bit NCO
    • DDC Bypass With Full Rate Output Up to 500 MSPS
  • Differential Full-Scale Input: 1.1 VPP
  • JESD204B Interface:
    • Subclass 1 Support
    • 1 Lane per ADC Up to 10 Gbps
    • Dedicated SYNC Pin for Pair of Channels
  • Support for Multi-Chip Synchronization
  • Spectral Performance:
    • fIN = 190-MHz IF at –1 dBFS:
      • SNR: 69 dBFS
      • NSD: –153 dBFS/Hz
      • SFDR: 86 dBc (HD2, HD3),
        95 dBFS (Non HD2, HD3)
    • fIN = 370-MHz IF at –3 dBFS:
      • SNR: 68.5 dBFS
      • NSD: –152.5 dBFS/Hz
      • SFDR: 80 dBc (HD2, HD3),
        86 dBFS (Non HD2, HD3)
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • Power Consumption: 625 mW/Ch, 2.5 W Total
  • Power Supplies: 1.15 V, 1.15 V, 1.9 V

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open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADS54J64 device is a quad-channel, 14-bit,
1-GSPS, analog-to-digital converter (ADC) offering wide-bandwidth, 2x oversampling and high SNR. The ADS54J64 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J64 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to a 200-MHz receive bandwidth. The ADS54J64 also supports a 14-bit, 500-MSPS output in DDC bypass mode.

A four-lane JESD204B interface simplifies connectivity, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 6
Type Title Date
* Datasheet ADS54J64 Quad-Channel, 14-Bit, 1-GSPS, 2x Oversampling, Analog-to-Digital Converter datasheet Oct. 09, 2017
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
User guides ADS54J64 Evaluation Module User's Guide Sep. 15, 2017
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Technical articles How to minimize filter loss when you drive an ADC Oct. 20, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description

The ADS54J64 evaluation module (EVM) is used to evaluate the ADS54J64 quad-channel, 14-bit, 1-GSPS, 2x-oversampling analog-to-digital converter (ADC). The EVM has transformer-coupled analog inputs to accommodate a wide range of signal sources and frequencies. The EVM is designed to connect (...)

Features
  • Transformer-coupled input network provides single-ended to differential signal conversion
  • LMK04828 (ultra-low jitter and phase noise clock) generates a complete JESD204B subclass 1 clocking solution simplifying the FPGA interface
  • Device registers programmed through a USB connector and FTDI USB-to-SPI (...)

Design tools & simulation

SIMULATION MODELS Download
SBAM344.ZIP (2273 KB) - IBIS-AMI Model
SIMULATION MODELS Download
SBAM345.ZIP (38 KB) - IBIS Model
SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
VQFN (RMP) 72 View options

Ordering & quality

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